SBASAK1A August   2022  â€“ December 2022 DAC82002

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 DAC Transfer Function
        2. 7.3.1.2 DAC Register Structure
      2. 7.3.2 Power-On Reset (POR)
      3. 7.3.3 Hardware Reset
      4. 7.3.4 Software Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
        1. 7.5.1.1 SYNC Interrupt
    6. 7.6 Register Maps
      1. 7.6.1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Arbitrary Waveform Generator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Bipolar Analog Output Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 Registers

Table 7-2 DAC82002 Registers
Offset Register Description Section
0h No Operation NOOP Register
2h Synchronization SYNC Register
5h Trigger TRIGGER Register
6h Broadcast BRDCAST Register
8h DAC-A DAC-A Register
9h DAC-B DAC-B Register

7.6.1.1 NOOP Register (offset = 0h) [reset = 0000h]

Figure 7-4 NOOP Register
1514131211109876543210
NOOP
W-0h
Table 7-3 NOOP Register Field Descriptions
Bit Field Type Reset Description
15-0 NOOP W 0h No operation command

7.6.1.2 SYNC Register (offset = 2h) [reset = 0300h]

Figure 7-5 SYNC Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DAC-B-BRDCAST-EN DAC-A-BRDCAST-EN RESERVED DAC-B-SYNC-EN DAC-A-SYNC-EN
W-0h W-1h W-1h W-0h W-0h W-0h
Table 7-4 SYNC Register Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED W 0h These bits are reserved.
9 DAC-B-BRDCAST-EN W 1h When set to 1, the corresponding DAC is set to update the output after a serial interface write to the BRDCAST register.
When cleared to 0, the corresponding DAC output remains unaffected after a serial interface write to the BRDCAST register.
8 DAC-A-BRDCAST-EN W 1h When set to 1, the corresponding DAC is set to update the output after a serial interface write to the BRDCAST register.
When cleared to 0, the corresponding DAC output remains unaffected after a serial interface write to the BRDCAST register.
7-2 RESERVED W 0h These bits are reserved.
1 DAC-B-SYNC-EN W 0h When set to 1, the DAC output is set to update in response to an LDAC trigger (synchronous mode).
When cleared to 0, the DAC output is set to update immediately (asynchronous mode), default.
0 DAC-A-SYNC-EN W 0h When set to 1, the DAC output is set to update in response to an LDAC trigger (synchronous mode).
When cleared to 0 ,the DAC output is set to update immediately (asynchronous mode), default.

7.6.1.3 TRIGGER Register (offset = 5h) [reset = 0000h]

Figure 7-6 TRIGGER Register
1514131211109876543210
RESERVEDLDACSOFT-RESET [3:0]
W-0hW-0hW-0h
Table 7-5 TRIGGER Register Field Descriptions
Bit Field Type Reset Description
15-5 RESERVED W 0h These bits are reserved.
4 LDAC W 0h Set this bit to 1 to synchronously load the DACs that are set to synchronous mode in the SYNC register. This bit self-resets.
3-0 SOFT-RESET [3:0] W 0h When set to reserved code 1010, this bit resets the device to the default state. This bit self-resets.

7.6.1.4 BRDCAST Register (offset = 6h) [reset = 0000h when RSTSEL is logic low, or reset = 8000h when RSTSEL is logic high]

Figure 7-7 BRDCAST Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRDCAST-DATA [15:0]
W-0000h when RSTSEL is logic low or 8000h when RSTSEL is logic high
Table 7-6 BRDCAST Register Field Descriptions
Bit Field Type Reset Description
15-0 BRDCAST-DATA [15:0] W 0000h when RSTSEL is logic low
or
8000h when RSTSEL is logic high		 Writing to the BRDCAST register forces the DAC channels that are set to broadcast from the SYNC register to update the active register data to the BRDCAST-DATA bits.

7.6.1.5 DAC-n Register (offset = 8h–9h) [reset = 0000h when RSTSEL is logic low, or reset = 8000h when RSTSEL is logic high]

Figure 7-8 DAC-n Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC-n-DATA [15:0]
W-0000h when RSTSEL is logic low or 8000h when RSTSEL is logic high
Table 7-7 DAC-A Data Register Field Descriptions (8h)
Bit Field Type Reset Description
15-0 DAC-A-DATA [15:0] W 0000h when RSTSEL is logic low
or
8000h when RSTSEL is logic high

Data are MSB aligned in straight binary format.
Table 7-8 DAC-B Data Register Field Descriptions (9h)
Bit Field Type Reset Description
15-0 DAC-B-DATA [15:0] W 0000h when RSTSEL is logic low
or
8000h when RSTSEL is logic high

Data are MSB aligned in straight binary format.