SBAS439C August   2008  – July 2015 DAC8311 , DAC8411

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: 14-Bit
    7. 7.7 Timing Requirements: 16-Bit
    8. 7.8 Typical Characteristics
      1. 7.8.1 Typical Characteristics: AVDD = 5 V
      2. 7.8.2 Typical Characteristics: AVDD = 3.6 V
      3. 7.8.3 Typical Characteristics: AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset to Zero-Scale
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 DAC8311 Serial Interface
        1. 8.5.1.1 DAC8311 Input Shift Register
        2. 8.5.1.2 DAC8311 SYNC Interrupt
      2. 8.5.2 DAC8411 Serial Interface
        1. 8.5.2.1 DAC8411 Input Shift Register
        2. 8.5.2.2 DAC8411 SYNC Interrupt
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Microprocessor Interfacing
        1. 9.1.1.1 DAC8x11 to 8051 Interface
        2. 9.1.1.2 DAC8x11 to Microwire Interface
        3. 9.1.1.3 DAC8x11 to 68HC11 Interface
    2. 9.2 Typical Applications
      1. 9.2.1 Loop Powered Transmitter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Using the REF5050 as a Power Supply for the DAC8x11
      3. 9.2.3 Bipolar Operation Using the DAC8x11
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage AVDD to GND –0.3 6 V
Digital input voltage to GND –0.3 AVDD +0.3 V
VOUT to GND –0.3 AVDD +0.3 V
Temperature Junction, TJ max 150 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TA Operating temperature –40 +125 °C
AVDD Supply voltage 2.0 +5.5 V

7.4 Thermal Information

THERMAL METRIC(1) DAC8x11 UNIT
DCK (SC70)
6 PINS
RθJA Junction-to-ambient thermal resistance 216.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.1 °C/W
RθJB Junction-to-board thermal resistance 65.9 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 65.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

at AVDD = 2 V to 5.5 V, RL = 2 kΩ to GND, and CL = 200 pF to GND, and TA = –40°C to +125°C unless otherwise noted.
PARAMETER TEST CONDITIONS DAC8411, DAC8311 UNIT
MIN TYP MAX
STATIC PERFORMANCE(1)
DAC8411 Resolution 16 Bits
Relative accuracy Measured by the line passing through codes 485 and 64714 3.6 V to 5 V ±4 ±8 LSB
2 V to 3.6 V ±4 ±12
Differential nonlinearity ±0.5 ±2 LSB
DAC8311 Resolution 14 Bits
Relative accuracy Measured by the line passing through codes 120 and 16200 ±1 ±4 LSB
Differential nonlinearity ±0.125 ±1 LSB
Offset error Measured by the line passing through two codes(2) ±0.05 ±4 mV
Offset error drift 3 μV/°C
Zero code error All zeros loaded to the DAC register 0.2 mV
Full-scale error All ones loaded to DAC register 0.04 0.2 % of FSR
Gain error 0.05 ±0.15 % of FSR
Gain temperature coefficient AVDD = 5 V ±0.5 ppm of FSR/°C
AVDD = 2 V ±1.5
OUTPUT CHARACTERISTICS
Output voltage range 0 AVDD V
Output voltage settling time(3) RL = 2 kΩ, CL = 200 pF, AVDD = 5 V,
1/4 scale to 3/4 scale		 6 10 μs

RL = 2 MΩ, CL = 470 pF 		12 μs
Slew rate 0.7 V/μs
Capacitive load stability RL = ∞ 470 pF
RL = 2 kΩ 1000 pF
Code change glitch impulse 1LSB change around major carry 0.5 nV-s
Digital feedthrough 0.5 nV-s
Power-on glitch impulse RL = 2 kΩ, CL = 200 pF, AVDD = 5 V 17 mV
DC output impedance 0.5 Ω
Short-circuit current AVDD = 5 V 50 mA
AVDD = 3 V 20 mA
Power-up time Coming out of power-down mode 50 μs
AC PERFORMANCE
SNR TA= 25°C, BW = 20 kHz, 16-bit level, AVDD = 5 V,
fOUT = 1 kHz, 1st 19 harmonics removed for SNR calculation		 88 dB
THD –66 dB
SFDR 66 dB
SINAD 66 dB
DAC output noise density(4) TA= 25°C, at zero-scale input,
fOUT = 1 kHz, AVDD = 5 V		 17 nV/√Hz
TA= 25°C, at mid-code input,
fOUT = 1 kHz, AVDD = 5 V		 110 nV/√Hz
DAC output noise(5) TA= 25°C, at mid-code input,
0.1 Hz to 10 Hz, AVDD = 5 V		 3 μVpp
LOGIC INPUTS(3)
Input current ±1 μA
VINL, input low voltage AVDD = 2.7 V to 5.5 V 0.3 × AVDD V
AVDD = 2 V to 2.7 V 0.1 × AVDD V
VINH, input high voltage AVDD = 2.7 V to 5.5 V 0.7 × AVDD V
AVDD = 2 V to 2.7 V 0.9 × AVDD V
Pin capacitance 1.5 3 pF
POWER REQUIREMENTS
AVDD 2 5.5 V
IDD Normal mode VINH = AVDD and VINL = GND, at mid-scale code(6) AVDD = 3.6 V to 5.5 V 110 160 μA
AVDD = 2.7 V to 3.6 V 95 150
AVDD = 2 V to 2.7 V 80 140
All power-down mode VINH = AVDD and VINL = GND, at mid-scale code(6) AVDD = 3.6 V to 5.5 V 0.5 3.5 μA
AVDD = 2.7 V to 3.6 V 0.4 3.0
AVDD = 2 V to 2.7 V 0.1 2.0
Power dissipation Normal mode VINH = AVDD and VINL = GND, at mid-scale code(6) AVDD = 3.6 V to 5.5 V 0.55 0.88 mW
AVDD = 2.7 V to 3.6 V 0.25 0.54
AVDD = 2 V to 2.7 V 0.14 0.38
All power-down mode VINH = AVDD and VINL = GND, at mid-scale code(6) AVDD = 3.6 V to 5.5 V 2.50 19.2 μW
AVDD = 2.7 V to 3.6 V 1.08 10.8
AVDD = 2 V to 2.7 V 0.72 8.1
(1) Linearity calculated using a reduced code range of 485 to 64714 for 16-bit, and 120 to 16200 for 14-bit, output unloaded.
(2) Straight line passing through codes 485 and 64714 for 16-bit, and 120 and 16200 for 14-bit, output unloaded.
(3) Specified by design and characterization, not production tested.
(4) For more details, see Figure 33.
(5) For more details, see Figure 34.
(6) For more details, see Figure 14 and Figure 55.

7.6 Timing Requirements: 14-Bit

All specifications at –40°C to 125°C, and AVDD = 2 V to 5.5 V, unless otherwise noted.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(SCLK) Serial clock frequency AVDD = 2.0 V to 3.6 V 20 MHz
AVDD = 3.6 V to 5.5 V 50
t1 SCLK cycle time AVDD = 2 V to 3.6 V 50 ns
AVDD = 3.6 V to 5.5 V 20
t2 SCLK high time AVDD = 2 V to 3.6 V 25 ns
AVDD = 3.6 V to 5.5 V 10
t3 SCLK low time AVDD = 2 V to 3.6 V 25 ns
AVDD = 3.6 V to 5.5 V 10
t4 SYNC to SCLK rising edge setup time AVDD = 2 V to 3.6 V 0 ns
AVDD = 3.6 V to 5.5 V 0
t5 Data setup time AVDD = 2 V to 3.6 V 5 ns
AVDD = 3.6 V to 5.5 V 5
t6 Data hold time AVDD = 2 V to 3.6 V 4.5 ns
AVDD = 3.6 V to 5.5 V 4.5
t7 SCLK falling edge to SYNC rising edge AVDD = 2 V to 3.6 V 0 ns
AVDD = 3.6 V to 5.5 V 0
t8 Minimum SYNC high time AVDD = 2 V to 3.6 V 50 ns
AVDD = 3.6 V to 5.5 V 20
t9 16th SCLK falling edge to SYNC falling edge AVDD = 2 V to 3.6 V 100 ns
AVDD = 3.6 V to 5.5 V 100
t10 SYNC rising edge to 16th SCLK falling edge
(for successful SYNC interrupt)		 AVDD = 2 V to 3.6 V 15 ns
AVDD = 3.6 V to 5.5 V 15
(1) All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Figure 1 timing diagram.

7.7 Timing Requirements: 16-Bit

All specifications at –40°C to 125°C, and AVDD = 2 V to 5.5 V, unless otherwise noted.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(SCLK) Serial clock frequency AVDD = 2.0 V to 3.6 V 20 MHz
AVDD = 3.6 V to 5.5 V 50
t1 SCLK cycle time AVDD = 2 V to 3.6 V 50 ns
AVDD = 3.6 V to 5.5 V 20
t2 SCLK high time AVDD = 2 V to 3.6 V 25 ns
AVDD = 3.6 V to 5.5 V 10
t3 SCLK low time AVDD = 2 V to 3.6 V 25 ns
AVDD = 3.6 V to 5.5 V 10
t4 SYNC to SCLK rising edge setup time AVDD = 2 V to 3.6 V 0 ns
AVDD = 3.6 V to 5.5 V 0
t5 Data setup time AVDD = 2 V to 3.6 V 5 ns
AVDD = 3.6 V to 5.5 V 5
t6 Data hold time AVDD = 2 V to 3.6 V 4.5 ns
AVDD = 3.6 V to 5.5 V 4.5
t7 SCLK falling edge to SYNC rising edge AVDD = 2 V to 3.6 V 0 ns
AVDD = 3.6 V to 5.5 V 0
t8 Minimum SYNC high time AVDD = 2 V to 3.6 V 50 ns
AVDD = 3.6 V to 5.5 V 20
t9 24th SCLK falling edge to SYNC falling edge AVDD = 2 V to 3.6 V 100 ns
AVDD = 3.6 V to 5.5 V 100
t10 SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)		 AVDD = 2 V to 3.6 V 15 ns
AVDD = 3.6 V to 5.5 V 15
(1) All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Figure 2 timing diagram.
DAC8311 DAC8411 tim_ser_14-bit_bas439.gifFigure 1. Serial Write Operation: 14-Bit (DAC8311)
DAC8311 DAC8411 tim_ser_16-bit_bas439.gifFigure 2. Serial Write Operation: 16-Bit (DAC8411)

7.8 Typical Characteristics

7.8.1 Typical Characteristics: AVDD = 5 V

at TA = 25°C, AVDD = 5 V, and DAC loaded with mid-scale code, unless otherwise noted.
DAC8311 DAC8411 tc_le_5v_40_bas439.gif
Figure 3. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)
DAC8311 DAC8411 tc_le_5v_25_bas439.gif
Figure 5. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (25°C)
DAC8311 DAC8411 tc_le_5v_125_bas439.gif
Figure 7. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (125°C)
DAC8311 DAC8411 tc_zc_error-tmp_5v_bas439.gif
Figure 9. Zero-Code Error vs Temperature
DAC8311 DAC8411 tc_offset-tmp_5v_bas439.gif
Figure 11. Offset Error vs Temperature
DAC8311 DAC8411 tc_fs_error-tmp_5v_bas439.gif
Figure 13. Full-Scale Error vs Temperature
DAC8311 DAC8411 tc_idd-tmp_5v_bas439.gif
Figure 15. Power-Supply Current vs Temperature
DAC8311 DAC8411 tc_is-logic_55v_bas439.gif
Figure 17. Power-Supply Current vs Logic Input Voltage
DAC8311 DAC8411 tc_thd_frq_5v_bas439.gif
Figure 19. Total Harmonic Distortion vs Output Frequency
DAC8311 DAC8411 tc_pwr_density_5v_bas439.gif
Figure 21. Power Spectral Density
DAC8311 DAC8411 tc_gltch_5v_16_ris_bas439.gif
Figure 23. Glitch Energy 5 V, 16-Bit, 1LSB Step, Rising Edge
DAC8311 DAC8411 tc_gltch_5v_14_ris_bas439.gif
Figure 25. Glitch Energy 5 V, 14-Bit, 1LSB Step, Rising Edge
DAC8311 DAC8411 tc_fs_5v_ris_bas439.gif
Figure 27. Full-Scale Settling Time 5-V Rising Edge
DAC8311 DAC8411 tc_hs_5v_ris_bas439.gif
Figure 29. Half-Scale Settling Time 5-V Rising Edge
DAC8311 DAC8411 tc_gltch_pwron_5v_bas439.gif
Figure 31. Power-On Reset to 0 V Power-On Glitch
DAC8311 DAC8411 tc_noise-frq_5v_bas439.gif
Figure 33. DAC Output Noise Density vs Frequency
DAC8311 DAC8411 tc_idd-vdd_bas439.gif
Figure 35. Power-Supply Current vs Power-Supply Voltage
DAC8311 DAC8411 tc_le_5v_14bit_40_bas439.gif
Figure 4. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)
DAC8311 DAC8411 tc_le_5v_14bit_25_bas439.gif
Figure 6. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (25°C)
DAC8311 DAC8411 tc_le_5v_14bit_125_bas439.gif
Figure 8. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (125°C)
DAC8311 DAC8411 tc_source_pos_5v_bas439.gif
Figure 10. Source Current at Positive Rail
DAC8311 DAC8411 tc_sink_neg_5v_bas439.gif
Figure 12. Sink Current at Negative Rail
DAC8311 DAC8411 tc_idd-code_55v_bas439.gif
Figure 14. Power-Supply Current vs Digital Input Code
DAC8311 DAC8411 tc_ipd-tmp_5v_bas439.gif
Figure 16. Power-Down Current vs Temperature
DAC8311 DAC8411 tc_histo_55v_bas439.gif
Figure 18. Power-Supply Current Histogram
DAC8311 DAC8411 tc_snr_frq_5v_bas439.gif
Figure 20. Signal-to-Noise Ratio vs Output Frequency
DAC8311 DAC8411 tc_clk_fdthru_5v_bas439.gif
Figure 22. Clock Feedthrough 5 V, 2 mHz, Midscale
DAC8311 DAC8411 tc_gltch_5v_16_fal_bas439.gif
Figure 24. Glitch Energy 5 V, 16-Bit, 1LSB Step, Falling Edge
DAC8311 DAC8411 tc_gltch_5v_14_fal_bas439.gif
Figure 26. Glitch Energy 5 V, 14-Bit, 1LSB Step, Falling Edge
DAC8311 DAC8411 tc_fs_5v_fal_bas439.gif
Figure 28. Full-Scale Settling Time 5-V Falling Edge
DAC8311 DAC8411 tc_hs_5v_fal_bas439.gif
Figure 30. Half-Scale Settling Time 5-V Falling Edge
DAC8311 DAC8411 tc_gltch_pwroff_5v_bas439.gif
Figure 32. Power-Off Glitch
DAC8311 DAC8411 tc_dac_noise_5v_bas439.gif
Figure 34. DAC Output Noise 0.1 Hz to 10 Hz Bandwidth
DAC8311 DAC8411 tc_ipd-vdd_bas439.gif
Figure 36. Power-Down Current vs Power-Supply Voltage

7.8.2 Typical Characteristics: AVDD = 3.6 V

at TA = 25°C, and AVDD = 3.6 V, unless otherwise noted.
DAC8311 DAC8411 tc_idd-code_36v_bas439.gif
Figure 37. Power-Supply Current vs Digital Input Code
DAC8311 DAC8411 tc_is-logic_36v_bas439.gif
Figure 39. Power-Supply Current vs Logic Input Voltage
DAC8311 DAC8411 tc_source_pos_36v_bas439.gif
Figure 41. Source Current at Positive Rail
DAC8311 DAC8411 tc_histo_36v_bas439.gif
Figure 43. Power-Supply Current Histogram
DAC8311 DAC8411 tc_idd-tmp_36v_bas439.gif
Figure 38. Power-Supply Current vs Temperature
DAC8311 DAC8411 tc_ipd-tmp_36v_bas439.gif
Figure 40. Power-Down Current vs Temperature
DAC8311 DAC8411 tc_sink_neg_36v_bas439.gif
Figure 42. Sink Current at Negative Rail

7.8.3 Typical Characteristics: AVDD = 2.7 V

at TA = 25°C, and AVDD = 2.7 V, unless otherwise noted.
DAC8311 DAC8411 tc_le_27v_40_bas439.gif
Figure 44. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)
DAC8311 DAC8411 tc_le_27v_25_bas439.gif
Figure 46. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (25°C)
DAC8311 DAC8411 tc_le_27v_125_bas439.gif
Figure 48. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (125°C)
DAC8311 DAC8411 tc_zc_error-tmp_27v_bas439.gif
Figure 50. Zero-Code Error vs Temperature
DAC8311 DAC8411 tc_offset-tmp_27v_bas439.gif
Figure 52. Offset Error vs Temperature
DAC8311 DAC8411 tc_fs_error-tmp_27v_bas439.gif
Figure 54. Full-Scale Error vs Temperature
DAC8311 DAC8411 tc_idd-tmp_27v_bas439.gif
Figure 56. Power-Supply Current vs Temperature
DAC8311 DAC8411 tc_is-logic_27v_bas439.gif
Figure 58. Power-Supply Current vs Logic Input Voltage
DAC8311 DAC8411 tc_thd_frq_27v_bas439.gif
Figure 60. Total Harmonic Distortion vs Output Frequency
DAC8311 DAC8411 tc_pwr_density_27v_bas439.gif
Figure 62. Power Spectral Density
DAC8311 DAC8411 tc_gltch_27v_16_ris_bas439.gif
Figure 64. Glitch Energy 2.7 V, 16-Bit, 1LSB Step, Rising Edge
DAC8311 DAC8411 tc_gltch_27v_14_ris_bas439.gif
Figure 66. Glitch Energy 2.7 V, 14-Bit, 1LSB Step, Rising Edge
DAC8311 DAC8411 tc_fs_27v_ris_bas439.gif
Figure 68. Full-Scale Settling Time 2.7 V Rising Edge
DAC8311 DAC8411 tc_hs_27v_ris_bas439.gif
Figure 70. Half-Scale Settling Time 2.7 V Rising Edge
DAC8311 DAC8411 tc_gltch_pwron_27v_bas439.gif
Figure 72. Power-On Reset to 0-V Power-On Glitch
DAC8311 DAC8411 tc_le_27v_14bit_40_bas439.gif
Figure 45. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)
DAC8311 DAC8411 tc_le_27v_14bit_25_bas439.gif
Figure 47. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (25°C)
DAC8311 DAC8411 tc_le_27v_14bit_125_bas439.gif
Figure 49. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (125°C)
DAC8311 DAC8411 tc_source_pos_27v_bas439.gif
Figure 51. Source Current at Positive Rail
DAC8311 DAC8411 tc_sink_neg_27v_bas439.gif
Figure 53. Sink Current at Negative Rail
DAC8311 DAC8411 tc_idd-code_27v_bas439.gif
Figure 55. Power-Supply Current vs Digital Input Code
DAC8311 DAC8411 tc_ipd-tmp_27v_bas439.gif
Figure 57. Power-Down Current vs Temperature
DAC8311 DAC8411 tc_histo_27v_bas439.gif
Figure 59. Power-Supply Current Histogram
DAC8311 DAC8411 tc_snr_frq_27v_bas439.gif
Figure 61. Signal-to-Noise Ratio vs Output Frequency
DAC8311 DAC8411 tc_clk_fdthru_27v_bas439.gif
Figure 63. Clock Feedthrough 2.7 V, 20 mHz, Midscale
DAC8311 DAC8411 tc_gltch_27v_16_fal_bas439.gif
Figure 65. Glitch Energy 2.7 V, 16-Bit, 1LSB Step, Falling Edge
DAC8311 DAC8411 tc_gltch_27v_14_fal_bas439.gif
Figure 67. Glitch Energy 2.7 V, 14-Bit, 1LSB Step, Falling Edge
DAC8311 DAC8411 tc_fs_27v_fal_bas439.gif
Figure 69. Full-Scale Settling Time 2.7 V Falling Edge
DAC8311 DAC8411 tc_hs_27v_fal_bas439.gif
Figure 71. Half-Scale Settling Time 2.7 V Falling Edge
DAC8311 DAC8411 tc_gltch_pwroff_27v_bas439.gif
Figure 73. Power-Off Glitch