DLPS119B December   2018  – May 2022 DLP2010NIR

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
      1. 6.13.1 Software Requirements
    14. 6.14 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FQJ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(10)

PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT
CURRENT
IDD Supply current: VDD(3) (5) VDD = 1.95 V 34.7 mA
VDD = 1.8 V 27.5
IDDI Supply current: VDDI(3) (5) VDDI = 1.95 V 9.4 mA
VDD = 1.8 V 6.6
IOFFSET Supply current: VOFFSET(4) (6) VOFFSET = 10.5 V 1.7 mA
VOFFSET = 10 V 0.9
IBIAS Supply current: VBIAS(4) (6) VBIAS = 18.5 V 0.4 mA
VBIAS = 18 V 0.2
IRESET Supply current: VRESET(6) VRESET = –14.5 V 2 mA
VRESET = –14 V 1.2
POWER(1)
PDD Supply power dissipation: VDD(3) (5) VDD = 1.95 V 67.7 mW
VDD = 1.8 V 49.5
PDDI Supply power dissipation: VDDI(3) (5) VDDI = 1.95 V 18.3 mW
VDD = 1.8 V 11.9
POFFSET Supply power dissipation: VOFFSET(4) (6) VOFFSET = 10.5 V 17.9 mW
VOFFSET = 10 V 9
PBIAS Supply power dissipation: VBIAS(4) (6) VBIAS = 18.5 V 7.4 mW
VBIAS = 18 V 3.6
PRESET Supply power dissipation: VRESET(6) VRESET = –14.5 V 29 mW
VRESET = –14 V 16.8
PTOTAL Supply power dissipation: Total 90.8 140.3 mW
LPSDR INPUT(7)
VIH(DC) DC input high voltage(9) 0.7 × VDD VDD + 0.3 V
VIL(DC) DC input low voltage(9) –0.3 0.3 × VDD V
VIH(AC) AC input high voltage(9) 0.8 × VDD VDD + 0.3 V
VIL(AC) AC input low voltage(9) –0.3 0.2 × VDD V
∆VT Hysteresis ( VT+ – VT– ) Figure 6-10 0.1 × VDD 0.4 × VDD V
IIL Low–level input current VDD = 1.95 V; VI = 0 V –100 nA
IIH High–level input current VDD = 1.95 V; VI = 1.95 V 100 nA
LPSDR OUTPUT(8)
VOH DC output high voltage IOH = –2 mA 0.8 × VDD V
VOL DC output low voltage IOL = 2 mA 0.2 × VDD V
CAPACITANCE
CIN Input capacitance LPSDR ƒ = 1 MHz 10 pF
Input capacitance SubLVDS ƒ = 1 MHz 20 pF
COUT Output capacitance ƒ = 1 MHz 10 pF
CRESET Reset group capacitance ƒ = 1 MHz; (480 × 108) micromirrors 95 113 pF
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
Supply power dissipation based on non–compressed commands and data.
Supply power dissipation based on 3 global resets in 200 µs.
LPSDR specifications are for pins LS_CLK and LS_WDATA.
LPSDR specification is for pin LS_RDATA.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR)JESD209B.
Device electrical characteristics are over Section 6.4 unless otherwise noted.