DLPS047B September   2014  – October 2015 DLPA2005

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Data Transmission Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DMD Regulators
      2. 7.3.2  RGB Strobe Decoder
      3. 7.3.3  LED Current Control
      4. 7.3.4  Maximum Led Currents and Efficiency Considerations
      5. 7.3.5  Calculating Inductor Peak Current
      6. 7.3.6  LED Current Accuracy
      7. 7.3.7  Transient Current Limiting
      8. 7.3.8  1.1-V Regulator (Buck Converter)
      9. 7.3.9  Measurement System
      10. 7.3.10 Protection Circuits
        1. 7.3.10.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)
        2. 7.3.10.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)
        3. 7.3.10.3 DMD Regulator Fault (DMD_FLT)
        4. 7.3.10.4 V6V Power-Good (V6V_PGF) Fault
        5. 7.3.10.5 VLED Overvoltage (VLED_OVP) Fault
        6. 7.3.10.6 VLED Power Save Mode
        7. 7.3.10.7 V1V8 PG Failure
        8. 7.3.10.8 Interrupt Pin (INTZ)
        9. 7.3.10.9 SPI
      11. 7.3.11 Password Protected Registers
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Projector Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Mobile Sensing Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Dlpc150 System Interfaces
          1. 8.3.2.1.1 Control Interface
      3. 8.3.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage at VINL, VINA, VINR, VINC –0.3 7 V
Ground pins to system ground –0.3 0.3 V
Voltage at SWN –18 7 V
Voltage at SWP, VBIAS –0.3 20 V
Voltage at VOFS –0.3 12 V
Voltage at V6V, VLED, L1, L2, SWC, SW4, SW5, SW6, INTZ, PROJ_ON –0.3 7 V
Voltage at all pins, unless noted otherwise –0.3 3.6 V
Source current RESETZ, CMP_OUT 1 mA
Source current SPI_DOUT 5.5 mA
Sink current RESETZ, CMP_OUT 1 mA
Sink current SPI_DOUT, INTZ 5.5 mA
Peak output current Internally limited
Continuous total power dissipation Internally limited by thermal shutdown
TJ Operating junction temperature –30 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).
MIN NOM MAX UNIT
Input voltage at VINL, VINA, VINR, VINC, Full functional and parametric performance 2.7 3.6 6 V
Extended operating range, limited parametric performance 2.3 3.6 6
Voltage at VSPI 1.65 1.8 3.6 V
Operational ambient temperature –10 85 °C
Operational junction temperature –10 120 °C

6.4 Thermal Information

THERMAL METRIC(1) DLPA2005 UNIT
RSL (48 PINS)
RθJA Junction-to-ambient thermal resistance(2) 27.9 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm × 114.3 mm, and 2-oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (see (1)(2)(4))
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLIES
INPUT VOLTAGE
VIN Input voltage range VINA, VINR, VINL, VINC 2.7 3.6 6 V
Extended input voltage range(1) 2.3 3.6 6
VLOW_BAT Low-battery warning threshold VINA falling 3 V
Hysteresis VINA rising 100 mV
Vhys(UVLO) Undervoltage lockout threshold VINA falling (through 5-bit trim function) 2.3 4.5 V
Hysteresis VINA rising 100 mV
VSTARTUP Startup voltage VBIAS, VOFS, VRST; loaded with 2 mA 2.5 V
INPUT CURRENT
IQ ACTIVE mode Motor current excluded 15 mA
ISTD STANDBY mode 900 µA
IIDLE IDLE mode 10 µA
INTERNAL SUPPLIES
VV6V Internal supply, analog 6.25 V
CLDO_V6V Filter capacitor for V6V LDO 100 nF
VV2V5 Internal supply, logic 2.5 V
CLDO_V2V5 Filter capacitor for V2V5 LDO 2.2 µF
DMD REGULATOR
RDS(ON) MOSFET ON-resistance Switch E (from VINR to SWN) 1000 mΩ
Switch F (from SWP to PGNDR) 320
VFW Forward voltage drop Switch G(2) (from SWP to VBIAS[2])
VINR = 5 V, VSWP = 2 V, IF = 100 mA		 1.3 V
Switch H (from SWP to VOFS)
VINR = 5 V, VSWP = 2 V, IF = 100 mA		 1.3
tDIS Rail discharge time VIN = 2.9 V; COUT = 110 nF 40 µs
tPG Power-good timeout Not tested in production 6 ms
ILIMIT Switch current limit 312 mA
L Inductor value 10 µH
VOFS REGULATOR
VOFS Output voltage 10 V
DC output voltage accuracy IOUT = 2 mA –2% 2%
DC load regulation VIN = 3.6 V, IOUT = 0 to 2 mA –19 V/A
DC line regulation VINA, VINL, VINR, VINC 2.7 to 6 V, IOUT = 2 mA 35 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF(3) 375 mVpp
IOUT Output current 0 3 mA
PG Power-good threshold
(fraction of nominal output voltage)		 VOFS rising 86%
VOFS falling 66%
RDIS Output discharge resistor Active when rail is disabled 100 Ω
COUT Output capacitor Recommended value (output capacitors for VOFS / VBIAS must be equal) 110 220 nF
tDISCHARGE < 40 µs at 2.9 V 100 110 nF
VBIAS REGULATOR
VBIAS Output voltage 18 V
DC output voltage accuracy IOUT = 2 mA –2% 2%
DC Load regulation VIN = 3.6 V, IOUT = 0 to 2 mA –14 V/A
DC Line regulation VINA, VINL, VINR, VINC 2.7 to 6 V, IOUT = 2 mA 18 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF (see (3)) 375 mVpp
IOUT Output current 0 4 mA
PG Power-good threshold
(fraction of nominal output voltage)		 VBIAS rising 86%
VBIAS falling 66%
RDIS Output discharge resistor Active when rail is disabled 100 Ω
COUT Output capacitor Recommended value (output capacitors for VOFS / VBIAS must be equal) 110 220 nF
tDISCHARGE < 40 µs at 2.9 V 100 110
VRST REGULATOR
VRST Output voltage –14 V
DC output voltage accuracy IOUT = 2 mA –3% 3%
DC load regulation VIN = 3.6 V, IOUT = 0 to 2 mA 13 V/A
DC line regulation VINA, VINL, VINR, VINC 2.7 to 6 V, IOUT = 2 mA –21 mV/V
VRIPPLE Output ripple VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF (see (3)) 375 mVpp
VREF_VRST Reference voltage 500 mV
IOUT Output current 0 4 mA
PG Power-good threshold (fraction of nominal output voltage) VRST rising 90%
VRST falling 90%
RDIS Output discharge resistor Active when rail is disabled ±150 Ω
COUT Output capacitor 110 220 nF
tDISCHARGE < 70 µs at VBAT ≥ 2.7 V 100 110
LED DRIVER
VLED BUCK-BOOST
VLED Output voltage range 1.2 5.4 V
Default output voltage SW4, SW5, SW6 in OPEN position 3.5
VOVP Output overvoltage protection Clamps buck-boost output 5.5 7 V
VLED_OVP Fault detection threshold Triggers VLED_OVP interrupt 5.4 V
ISW Switch current limit 3.5 4.0 4.5 A
RDS(ON) MOSFET ON-resistance Switch A (from VINL to L1) 50 mΩ
Switch B (from L1 to PGNDL) 50
Switch C (from L2 to PGNDL) 50
Switch D (from L2 to VLED) 50
fSW Switching frequency 2.25 MHz
COUT Output capacitance 2 × 22 µF
RGB STROBE CONTROLLER SWITCHES
RDS(ON) Drain-source ON-resistance SW4, SW5, SW6 30 75 mΩ
ILEAK OFF-state leakage current VDS = 5 V 1 µA
LED CURRENT CONTROL
Vƒ LED forward voltage 4.55 V
ILED LED Currents VIN ≥4.50 V, VLED ≤4.8 V; (closed loop operation)
Covers USB power and 5 V AC adapter
Current at max. code 0x3CBh for SWx_IDAC[9:0]
RLIM =39mΩ, 0.1%, TA ≤45°C (see register settings)		 2200 2400 2600 mA
VIN ≥ 2.7 V, VLED ≤4.8 V, (closed loop operation)
Covers single cell Li-ion battery with high current loading
Current at max. code 0x20Eh for SWx_IDAC[9:0]
RLIM = 39 mΩ, 0.1%, TA=25 C (see register settings) 		1300
DC current accuracy, SW4, 5, 6 RLIM = 39 mΩ ±100 mA
Transient LED current limit range ILIM[3:0] = 0000 at RLIM = 39 mΩ 333 mA
ILIM[3:0] = 1111 3846
trise Current rise time ILED from 5% to 95%, ILED = 300 mA,
Transient current limit disabled
Not tested in production		 50 µs
1.1-V REGULATOR
VCORE (BUCK)
VIN Input voltage 2.3 6 V
VOUT Nominal fixed output voltage 1.1 V
DC output voltage accuracy 0 mA ≤ IOUT ≤ 600 mA at VIN > 2.5 V
VOUT = 1.1 V 		–1.5% 1.5%
d Maximum duty cycle 100%
RDS(ON) Low-side MOSFET on-resistance VIN = 3.6 V, TJ = 27ºC 185 380 mΩ
High-side MOSFET on-resistance 240 480 mΩ
IOUT Output current VIN > 2.3 V 300 600 mA
ILIMIT Switch current limit 1 A
tSS Soft-start time Time to ramp from 10% to 90% of VOUT, VIN = 3.6 V 250 µs
COUT Output capacitance 10 µF
L Nominal Inductance 2.2 µH
LOAD SWITCH
VIN Input voltage range LS_IN 1.8 3.6 V
RDS(ON) P-channel MOSFET on-resistance VIN = 1.8 V, over full temperature range 340 385 mΩ
COUT Output capacitor Ceramic 4.7 10 12 µF
ESR of output capacitor Ceramic 5 20 500 mΩ
MEASUREMENT SYSTEM (AFE)
G Amplifier gain (PGA) AFE_GAIN[1:0] = 01 1.0 V/V
AFE_GAIN[1:0] = 10 9.5
AFE_GAIN[1:0] = 11 18
VOFS Input referred offset voltage PGA, AFE_CAL_DIS = 1
Not tested in production		 –1 1 mV
Comparator
Not tested in production		 –1.5 1.5
tsettle Settling time To 1% of final value (not tested in production) 15 µs
To 0.1% of final value (not tested in production) 52
ƒsample Sampling rate Not tested in production 19 kHz
LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL Output low-level IO = 0.5-mA sink current
(RESETZ, CMP_OUT)		 0 0.3 V
IO = 5-mA sink current
(SPI_DOUT, INTZ)		 0 0.3 × VSPI
VOH Output high-level IO = 0.5-mA source current
(RESETZ, CMP_OUT)		 1.3 2.5 V
IO = 5-mA source current
(SPI_DOUT)		 0.7 × VSPI VSPI
VIL Input low-level PROJ_ON, LED_SEL0, LED_SEL1 0 0.4 V
SPI_CSZ, SPI_CLK, SPI_DIN 0 0.3 × VSPI
VIH Input high-level PROJ_ON, LED_SEL0, LED_SEL1 1.2 V
SPI_CSZ, SPI_CLK, SPI_DIN 0.7 × VSPI VSPI
IBIAS Input bias current VIO = 3.3 V, any input pin 0.5 µA
tDEGLITCH Deglitch time PROJ_ON, (not tested in production) 1 ms
LED_SEL0, LED_SEL1 pins (not tested in production) 300 ns
INTERNAL OSCILLATOR
ƒOSC Oscillator frequency 9 MHz
Frequency accuracy TA = –30 to 85°C –10% 10%
THERMAL SHUTDOWN
TWARN Thermal warning (HOT threshold) 120 °C
Hysteresis 10
TSHTDWN Thermal shutdown (TSD threshold) 150 °C
Hysteresis 15
(1) Fully functional but limited parametric performance
(2) Including rectifying diode
(3) To reduce ripple the COUT can be increased. VRIPPLE is inversely proportional to COUT.
(4) Typicals are at 25 C.

6.6 Data Transmission Timing Requirements

VBAT = 3.6 ± 5%, TA = 25 ºC, CL = 10 pF (unless otherwise noted)
MIN TYP MAX UNIT
ƒCLK Serial clock frequency 0 36 MHz
tCLKL Pulse width low, SPI_CLK, 50% level 10 ns
tCLKH Pulse width high, SPI_CLK, 50% level 10 ns
tt Transition time, 20% to 80% level, all signals 0.2 4 ns
tCSCR SPI_CSZ falling to SPI_CLK rising, 50% level 8 ns
tCFCS SPI_CLK falling to SPI_CSZ rising, 50% level 1 ns
tCDS SPI_DIN data setup time, 50% level 7 ns
tCDH SPI_DIN data hold time, 50% level 6 ns
tiS SPI_DOUT data setup time(1)), 50% level 10 ns
tiH SPI_DOUT data hold time(1), 50% level 0 ns
tCFDO SPI_CLK falling to SPI_DOUT data valid, 50% level 13 ns
tCSZ SPI_CSZ rising to SPI_DOUT HiZ 6 ns
(1) The DLPC3430/DLPC3435 processors send and receive data on the falling edge of the clock.
DLPA2005 tim_SPI_LPS043.gif Figure 1. SPI Timing Diagram

6.7 Typical Characteristics

The maximum output current of the buck-boost is a function of input voltage (VIN), and output voltage (VLED). The relationship between VIN, VLED, and MAX ILED is shown in Figure 2. Please note that VLED is the output of the buck-boost regulator, which includes the voltage drop across the sense resistor RLIM (39 mOhms typical), internal strobe control switch (75 mΩ max), and the forward voltage of the LED. For example, to drive 2.4 A of current through a LED with Vƒ = 4.8 V using the DLPA2005, the minimum input voltage needs to be 4.5 V.

DLPA2005 cmax_led_currents_.gif
2.3 V < VLED < 4.8 V
Figure 2. Maximum LED Output Current as a Function of
Input Voltage (VIN) and Buck-Boost Output Voltage (VLED)

NOTE

Measured on a typical unit. VLED is the output of the buck-boost regulator and includes the voltage drop across the sense resistor, internal strobe control switch, and the forward voltage of the LED.