SNLS647G december   2019  – july 2023 DP83826E , DP83826I

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Mode Comparison Tables
  7. Pin Configuration and Functions (ENHANCED Mode)
  8. Pin Configuration and Functions (BASIC Mode)
  9. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  10. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 9.3.2  Auto-MDIX Resolution
      3. 9.3.3  Energy Efficient Ethernet
        1. 9.3.3.1 EEE Overview
        2. 9.3.3.2 EEE Negotiation
      4. 9.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 9.3.5  Wake-on-LAN Packet Detection
        1. 9.3.5.1 Magic Packet Structure
        2. 9.3.5.2 Magic Packet Example
        3. 9.3.5.3 Wake-on-LAN Configuration and Status
      6. 9.3.6  Low Power Modes
        1. 9.3.6.1 Active Sleep
        2. 9.3.6.2 IEEE Power-Down
        3. 9.3.6.3 Deep Power Down State
      7. 9.3.7  RMII Repeater Mode
      8. 9.3.8  Clock Output
      9. 9.3.9  Media Independent Interface (MII)
      10. 9.3.10 Reduced Media Independent Interface (RMII)
      11. 9.3.11 Serial Management Interface
        1. 9.3.11.1 Extended Register Space Access
        2. 9.3.11.2 Write Address Operation
        3. 9.3.11.3 Read Address Operation
        4. 9.3.11.4 Write (No Post Increment) Operation
        5. 9.3.11.5 Read (No Post Increment) Operation
        6. 9.3.11.6 Example Write Operation (No Post Increment)
      12. 9.3.12 100BASE-TX
        1. 9.3.12.1 100BASE-TX Transmitter
          1. 9.3.12.1.1 Code-Group Encoding and Injection
          2. 9.3.12.1.2 Scrambler
          3. 9.3.12.1.3 NRZ to NRZI Encoder
          4. 9.3.12.1.4 Binary to MLT-3 Converter
        2. 9.3.12.2 100BASE-TX Receiver
      13. 9.3.13 10BASE-Te
        1. 9.3.13.1 Squelch
        2. 9.3.13.2 Normal Link Pulse Detection and Generation
        3. 9.3.13.3 Jabber
        4. 9.3.13.4 Active Link Polarity Detection and Correction
      14. 9.3.14 Loopback Modes
        1. 9.3.14.1 Near-end Loopback
        2. 9.3.14.2 MII Loopback
        3. 9.3.14.3 PCS Loopback
        4. 9.3.14.4 Digital Loopback
        5. 9.3.14.5 Analog Loopback
        6. 9.3.14.6 Far-End (Reverse) Loopback
      15. 9.3.15 BIST Configurations
      16. 9.3.16 Cable Diagnostics
        1. 9.3.16.1 Time Domain Reflectometry (TDR)
        2. 9.3.16.2 Fast Link-Drop Functionality
      17. 9.3.17 LED and GPIO Configuration
    4. 9.4 Programming
      1. 9.4.1 Hardware Bootstraps Configuration
        1. 9.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 9.4.1.1.1 Bootstraps for PHY Address
        2. 9.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 9.4.1.2.1 Bootstraps for PHY Address
    5. 9.5 Register Maps
      1. 9.5.1 DP83826 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 10.2.2 Transformer Recommendations
      3. 10.2.3 Capacitive DC Blocking
      4. 10.2.4 Design Requirements
        1. 10.2.4.1 Clock Requirements
          1. 10.2.4.1.1 Oscillator
          2. 10.2.4.1.2 Crystal
      5. 10.2.5 Detailed Design Procedure
        1. 10.2.5.1 MII Layout Guidelines
        2. 10.2.5.2 RMII Layout Guidelines
        3. 10.2.5.3 MDI Layout Guidelines
      6. 10.2.6 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
        1. 12.1.5.1 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions (ENHANCED Mode)

The ENHANCED mode is one of two modes that the DP83826 can be configured in at start-up. This mode allows the DP83826 to support real-time Ethernet applications in addition to the standard Ethernet applications. To configure the DP83826 to ENHANCED mode, leave ModeSelect (pin 1) unconnected or pull up with a resistor to VDDIO.

GUID-20210503-CA0I-GV4N-JTKR-CV44DXNJ240H-low.svgFigure 6-1 RHB Package
32-Pin QFN
(Top View)
Table 6-1 Pin Functions (ENHANCED Mode)
PINTYPE (1)DESCRIPTION
NAMENO
ModeSelect1Reset: I, PU Active: I, PUThis pin selects the DP83826 operating mode: BASIC mode or ENHANCED mode. For ENHANCED mode, this pin shall be left NC or pulled-up with a resistor to VDDIO. For BASIC mode, this pin shall be shorted to GND.
CEXT2AExternal capacitor: Connect the CEXT pin through a 2-nF capacitor to GND.
VDDA3V33PowerInput analog supply: 3V3. For decoupling capacitor requirements, refer to Power Supply Recommendations section of data sheet.
RD_M4ADifferential receive input (physical media dependent: PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX specific signaling mode.
RD_P5A
TD_M6ADifferential transmit output (PMD): These differential outputs are configured to either 10BASE-Te or 100BASE-TX signaling mode based on configuration chosen for PHY.
TD_P7A
XO8ACrystal output: Reference clock output. XO pin is used for crystal only. Leave this pin floating when a CMOS-level oscillator is connected to XI.
XI/50MHzIn9ACrystal or oscillator input clock:

MII mode, RMII master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock.

RMII slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock.

RBIAS10ARBIAS ( Bias resistor) value 6.49 kΩ with 1% precision connected to ground.
MDIO11Reset: I, PU Active: I/O, PUManagement data I/O: Bi-directional management data signal that may be sourced by the management station or the PHY. This pin has internal pullup resistor of 10 kΩ. An external pullup resistor can be added if needed.
MDC12Reset: I, PD Active: I, PDManagement data clock: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.
RX_D313Reset: I, PD Active: O

Strap7

Receive data: Symbols received on the cable are decoded and presented on these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is received in MII mode. 2-bits RX_D[1:0] is received in RMII mode.
RX_D214Reset: I, PD Active: O

Strap8

RX_D115Reset: I, PD Active: O

Strap9

RX_D016Reset: I, PD Active: O

Strap0

VDDIO17PowerI/O supply voltage: 3.3 V/1.8 V. For decoupling capacitor requirements, refer to Power Supply Decoupling Recommendations section of data sheet.
RX_DV/ CRS_DV18Reset: I, PD Active: O

Strap10

Receive data valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode and on RX_D[1:0] in RMII mode. In MII mode, this pin acts as RX_DV. In RMII mode, this pin acts as CRS_DV and combines the RMII Carrier and Receive Data Valid indications. This pin can be configured to RX_DV in RMII mode to enable RMII Repeater Mode.
RX_CLK/ 50MHz_RMII19Reset: I, PD Active: OMII receive clock: MII Receive Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received data stream.

In RMII Master mode, this provides 50-MHz reference clock. In RMII Slave mode, this pin is not used and remains Input, pulldown.

RX_ER20Reset: I, PD Active: O

Strap6

Receive error: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode.

In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK.

In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. RX_ER is asserted high for every reception error, including errors during Idle.

This strap only latches on power-up and not on pin reset.

PWRDN/INT21Reset: I, PU Active: I, PUPower down (default), interrupt: The default function of this pin is power down. Register access is required to configure this pin as an interrupt. In power down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup resistor (9.5 kΩ). Some applications may require an external PU resistor.
TX_CLK22Reset: I, PD Active: O

Strap5

MII transmit clock: MII transmit clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock has constant phase referenced to the input clock. Unused in RMII Mode.
TX_EN23Reset: I, PD Active: I, PDTransmit enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode. TX_EN is an active high signal.
TX_D024Reset: I, PD Active: I, PDTransmit data:

In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK.

In RMII mode, TX_D[1:0] received from the MAC is synchronous to the rising edge of the reference clock.

TX_D125Reset: I, PD Active: I, PD
TX_D226Reset: I, PD Active: I, PD
TX_D327Reset: I, PD Active: I, PD
COL/LED2/TX_ER GPIO28Reset: I, PD Active: O

Strap4

Collision Detect (default): In MII mode when the pin is acting as Collision Detect (COL), this pin is always LOW in Full Duplex mode. In Half Duplex mode, COL is asserted HIGH only when both transmit and receive media are non-idle. This pin can also be configured as a second additional LED driver (LED2), the MII TX_ER signal or general purpose I/O (GPIO) through register configurations.

In RMII mode, this pin acts as LED2 by default.

CRS/LED329Reset: I, PD Active: O

Strap3

Carrier sense (default):

In MII mode this pin is asserted high when the receive or transmit medium is non-idle. Carrier sense and receive data valid. This pin can be configured as third LED (LED3) through register configuration.

In RMII mode, it is configured as LED3 by default.

LED030Reset: I, PD Active: O

Strap2

LED0: This LED indicates transmit and receive activity in addition to the status of the Link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is active.

LED polarity is auto-detected (Active Low/ Active High) based on external pull-up or pull-down on the pin.

CLKOUT/ LED131Reset: I, PU Active: O

Strap1

This pin provides 25-MHz reference clock from XI as default output after power-on reset (POR). The output is not affected by Resets allowing Application to reset PHY without impacting other system getting impacted. The output clock switches off only by Deep Power Down.

The pin can be configured to act as LED1 using strap or register configuration. The strap only latches on power-up and not on pin reset. The LED is ON when link is 100 M. LED remains OFF if Link is 10 M or no Link.

LED polarity is auto-detected (Active Low/ Active High) based on external pull-up or pull-down on the pin.

This strap only latches on power-up and not on pin reset.

RST_N32Reset: I, PU Active: I, PUReset low: RST_N pin is an active low reset input. Asserting this pin low for at least 25 μs forces a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all the internal registers of the PHY to default value.
I = Input, O = Output, I/O = Input/Ouput, A = Analog, PU or PD = Internal pullup or pulldown: Hardware bootstrap configuration