Low latency 10/100-Mbps PHY with MII interface and enhanced mode
Product details
Parameters
Package | Pins | Size
Features
- Low and deterministic latency
- TX latency: 40 ns, RX latency: 170 ns
- Deterministic latency over power cycles < ±2 ns
- Fixed phase XI to TX_CLK relationship < ±2 ns
- Robust and small system solution
- Integrated circuitry for enhanced EMC
- IEC 61000-4-2 ESD: ±8 kV contact, ±15 kV air
- IEC 61000-4-4 EFT: ±4 kV @ 5 kHz, 100 kHz
- CISPR 22 conducted emissions Class B
- CISPR 22 radiated emissions Class B
- Fast link-drop < 10 µs
- Cable reach > 150 meters
- Voltage mode line driver
- Integrated terminations on MAC interface
- Voltage tolerance: ±10%
- Two selectable pin modes in single device
- ENHANCED mode for additional features
- BASIC mode for common Ethernet pinout
- Low power consumption < 160 mW
- MAC interfaces: MII, RMII
- Programmable energy-saving modes
- Active sleep
- Deep power down
- Energy Efficient Ethernet (EEE) IEEE 802.3az
- Wake-on-LAN (WoL)
- Diagnostic tools: cable diagnostics, built-in self-test (BIST), loopback modes
- Single, 3.3-V power supply
- I/O voltages: 1.8 V or 3.3 V
- RMII back-to-back repeater mode
- DP83826E operating temperature range: –40°C to 105°C
- DP83826I operating temperature range: –40°C to 85°C
- IEEE 802.3 compliant: 10BASE-Te, 100BASE-TX
Description
The DP83826 offers low and deterministic latency, low power and supports 10BASE-Te, 100BASE-TX Ethernet protocols to meet stringent requirements in real-time industrial Ethernet systems. The device includes hardware bootstraps to achieve fast link-up time, fast link-drop detection modes and dedicated reference CLKOUT to clock synchronize other modules on the systems.
The two configurable modes are BASIC standard Ethernet mode that uses a common Ethernet pinout, and ENHANCED Ethernet mode which supports standard Ethernet mode and multiple industrial Ethernet fieldbus applications with the additional features and hardware bootstraps configuration.
Similar products you might be interested in
Pin-for-pin with same functionality to the compared device.
Technical documentation
No results found. Please clear your search and try again.
View all 7 | Type | Title | Date | |
|---|---|---|---|
| * | Data sheet | DP83826E Deterministic,Low-Latency,Low-Power,10/100Mbps,Industrial Ethernet PHY datasheet (Rev. D) | Sep. 01, 2020 |
| Application note | How and Why to Use the DP83826E for EtherCAT® Applications (Rev. A) | Oct. 05, 2020 | |
| Technical article | A history of industrial Ethernet protocols and their benefits | Jul. 15, 2020 | |
| Technical article | SimpliPHY your Ethernet design, part 1: Ethernet PHY basics and selection process | Mar. 11, 2020 | |
| Application note | KSZ8081 to DP83826E System Rollover | Jan. 10, 2020 | |
| Technical article | Top 3 considerations for harsh industrial Ethernet | Nov. 04, 2019 | |
| Technical article | How to select the right industrial Ethernet standard: EtherCAT | Sep. 17, 2015 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The DP83826EVM is aimed at highlighting the low latency, deterministic, and low power DP83826 Ethernet PHY. It supports 100BASE-TX and 10BASE-Te Ethernet protocols. The evaluation board (EVM) provides a quick and easy platform to evaluate various features supported by DP83826. The EVM will have (...)
Features
- 150m Cat5 cable reach
- 100Base-TX, 10Base-Te
- On-Board MSP430F5529 with USB-2-MDIO for register access
- Supports interoperability testing, compliance testing and BER testing
Software development
ETHERNET-SW — The Linux drivers for Texas Instruments' Ethernet physical layer (PHY) transceivers support communication through the serial management interface (MDC/MDIO) to configure and read PHY registers.
The USB-2-MDIO software lets you directly access the registers during debug and prototyping. (...)
Design tools & simulation
SNLM241.ZIP (27 KB) - IBIS Model
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
TINA-TI — TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| VQFN (RHB) | 32 | View options |
Ordering & quality
Information included:
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.