SNOSAX1F May   2008  – September 2015 DP83849I

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 System Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 Pin Assignments
    2. 3.2 Signal Descriptions
      1. 3.2.1  Serial Management Interface
      2. 3.2.2  Clock Interface
      3. 3.2.3  MAC Data Interface
      4. 3.2.4  LED Interface
      5. 3.2.5  JTAG Interface
      6. 3.2.6  Reset and Power Down
      7. 3.2.7  Strap Options
      8. 3.2.8  PMD Interface for 10 Mb/s and 100 Mb/s
      9. 3.2.9  Special Connections
      10. 3.2.10 Power Supply Pins
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Specifications
    6. 4.6 AC Timing Requirements
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Auto-Negotiation Complete Time
        6. 5.3.1.6 Enabling Auto-Negotiation Through Software
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
      7. 5.3.7 Link Diagnostic Capabilities
        1. 5.3.7.1 Linked Cable Status
        2. 5.3.7.2 Polarity Reversal
          1. 5.3.7.2.1 Cable Swap Indication
          2. 5.3.7.2.2 100 MB Cable Length Estimation
          3. 5.3.7.2.3 Frequency Offset Relative to Link Partner
          4. 5.3.7.2.4 Cable Signal Quality Estimation
          5. 5.3.7.2.5 Link Quality Monitor
        3. 5.3.7.3 Link Quality Monitor Control and Status
          1. 5.3.7.3.1 Checking Current Parameter Values
          2. 5.3.7.3.2 Threshold Control
        4. 5.3.7.4 TDR Cable Diagnostics
          1. 5.3.7.4.1 TDR Pulse Generator
          2. 5.3.7.4.2 TDR Pulse Monitor
          3. 5.3.7.4.3 TDR Control Interface
          4. 5.3.7.4.4 TDR Results
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Preamble Suppression
        3. 5.4.3.3 Simultaneous Register Write
      4. 5.4.4 MAC Interface
        1. 5.4.4.1 10-Mb Serial Network Interface (SNI)
        2. 5.4.4.2 Single Clock MII Mode
        3. 5.4.4.3 Flexible MII Port Assignment
          1. 5.4.4.3.1 RX MII Port Mapping
          2. 5.4.4.3.2 TX MII Port Mapping
          3. 5.4.4.3.3 Common Flexible MII Port Configurations
        4. 5.4.4.4 Strapped Extender Mode
        5. 5.4.4.5 Notes and Restrictions
      5. 5.4.5 PHY Address
        1. 5.4.5.1 MII Isolate Mode
      6. 5.4.6 Half Duplex vs Full Duplex
      7. 5.4.7 Reset Operation
        1. 5.4.7.1 Hardware Reset
        2. 5.4.7.2 Full Software Reset
        3. 5.4.7.3 Soft Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
      2. 5.5.2 100BASE-TX Receiver
      3. 5.5.3 Analog Front End
        1. 5.5.3.1  Digital Signal Processor
        2. 5.5.3.2  Digital Adaptive Equalization and Gain Control
        3. 5.5.3.3  Signal Detect
        4. 5.5.3.4  MLT-3 to NRZI Decoder
        5. 5.5.3.5  NRZI to NRZ
        6. 5.5.3.6  Serial to Parallel
        7. 5.5.3.7  Descrambler
        8. 5.5.3.8  Code-Group Alignment
        9. 5.5.3.9  4B/5B Decoder
        10. 5.5.3.10 100BASE-TX Link Integrity Monitor
        11. 5.5.3.11 BAD SSD Detection
      4. 5.5.4 10BASE-T Transceiver Module
        1. 5.5.4.1  Operational Modes
        2. 5.5.4.2  Smart Squelch
        3. 5.5.4.3  Collision Detection and SQE
        4. 5.5.4.4  Carrier Sense
        5. 5.5.4.5  Normal Link Pulse Detection/Generation
        6. 5.5.4.6  Jabber Function
        7. 5.5.4.7  Automatic Link Polarity Detection and Correction
        8. 5.5.4.8  Transmit and Receive Filtering
        9. 5.5.4.9  Transmitter
        10. 5.5.4.10 Receiver
    6. 5.6 Register Block
      1. 5.6.1 Register Definition
        1. 5.6.1.1  Basic Mode Control Register (BMCR)
        2. 5.6.1.2  Basic Mode Status Register (BMSR)
        3. 5.6.1.3  PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4  PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5  Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7  Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8  Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9  Auto-Negotiation Next Page Transmit Register (ANNPTR)
        10. 5.6.1.10 PHY Status Register (PHYSTS)
        11. 5.6.1.11 MII Interrupt Control Register (MICR)
        12. 5.6.1.12 MII Interrupt Status and Miscellaneous Control Register (MICR)
        13. 5.6.1.13 Page Select Register (PAGESEL)
      2. 5.6.2 Extended Registers - Page 0
        1. 5.6.2.1  False Carrier Sense Counter Register (FCSCR)
        2. 5.6.2.2  Receiver Error Counter Register (RECR)
        3. 5.6.2.3  100 Mb/s PCS Configuration and Status Register (PCSR)
        4. 5.6.2.4  RMII and Bypass Register (RBR)
        5. 5.6.2.5  LED Direct Control Register (LEDCR)
        6. 5.6.2.6  PHY Control Register (PHYCR)
        7. 5.6.2.7  10BASE-T Status/Control Register (10BTSCR)
        8. 5.6.2.8  CD Test and BIST Extensions Register (CDCTRL1)
        9. 5.6.2.9  Phy Control Register 2 (PHYCR2)
        10. 5.6.2.10 Energy Detect Control (EDCR)
      3. 5.6.3 Link Diagnostics Registers - Page 2
        1. 5.6.3.1  100Mb Length Detect Register (LEN100_DET), Page 2, address 14h
        2. 5.6.3.2  100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h
        3. 5.6.3.3  TDR Control Register (TDR_CTRL), Page 2, address 16h
        4. 5.6.3.4  TDR Window Register (TDR_WIN), Page 2, address 17h
        5. 5.6.3.5  TDR Peak Register (TDR_PEAK), Page 2, address 18h
        6. 5.6.3.6  TDR Threshold Register (TDR_THR), Page 2, address 19h
        7. 5.6.3.7  Variance Control Register (VAR_CTRL), Page 2, address 1Ah
        8. 5.6.3.8  Variance Data Register (VAR_DATA), Page 2, address 1Bh
        9. 5.6.3.9  Link Quality Monitor Register (LQMR), Page 2, address 1Dh
        10. 5.6.3.10 Link Quality Data Register (LQDR), Page 2
  6. 6 Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 TPI Network Circuit
        2. 6.2.2.2 Clock In (X1) Requirements
          1. 6.2.2.2.1 Oscillator
          2. 6.2.2.2.2 Crystal
      3. 6.2.3 Power Feedback Circuit
      4. 6.2.4 Power Down/Interrupt
        1. 6.2.4.1 Power Down Control Mode
        2. 6.2.4.2 Interrupt Mechanisms
      5. 6.2.5 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layer Stacking
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Community Resources
      1. 9.1.1 Community Resources
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Terminal Configuration and Functions

The DP83849I pins are classified into the following interface categories (each interface is described in the sections that follow):

  • Serial Management Interface
  • MAC Data Interface
  • Clock Interface
  • LED Interface
  • JTAG Interface
  • Reset and Power Down
  • Strap Options
  • 10/100 Mb/s PMD Interface
  • Special Connect Pins
  • Power and Ground pins

NOTE

Strapping pin option. See Section 3.2.7 for strap definitions.

All DP83849I signal pins are I/O cells regardless of the particular use. The following definitions define the functionality of the I/O cells for each pin.

Type: I Input
Type: O Output
Type: I/O Input/Output
Type OD Open Drain
Type: PD, PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is to be changed then an external 2.2-kΩ resistor must be used. See Section 3.2.7 for details.)

PFC Package
80-Pin TQFP
Top View

DP83849I po_01_layout_snosax1.gif

3.1 Pin Assignments

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PIN NO. NAME PIN NO. NAME
1 CRS_A/CRS_DV_A/LED_CFG_A 41 LED_ACT/LED_COL/AN_EN_B
2 RX_ER_A/MDIX_EN_A 42 LED_SPEED_B/AN1_B
3 COL_A 43 LED_LINK_B/AN0_B
4 RXD0_A/PHYAD1 44 PWRDOWN_INT_B
5 RXD1_A/PHYAD2 45 TXD3_B/SNI_MODE_B
6 COREGND1 46 TXD2_B
7 PFBIN1 47 TXD1_B
8 RXD2_A/CLK2MAC_DIS 48 TXD0_B
9 RXD3_A/ED_EN_A 49 TX_EN_B
10 IOGND1 50 TX_CLK_B
11 IOVDD1 51 IOVDD2
12 TX_CLK_A 52 IOGND2
13 TX_EN_A 53 RXD3_B/ED_EN_B
14 TXD0_A 54 PFBIN4
15 TXD1_A 55 COREGND2
16 TXD2_A 56 RXD2_B/EXTENDER_EN
17 TXD3_A/SNI_MODE_A 57 RXD1_B/PHYAD4
18 PWRDOWN_INT_A 58 RXD0_B/PHYAD3
19 LED_LINK_A/AN0_A 59 COL_B
20 LED_SPEED_A/AN1_A 60 RX_ER_B/MDIX_EN_B
21 LED_ACT/LED_COL/AN_EN_A 61 CRS_B/CRS_DV_B/LED_CFG_B
22 ANAGND1 62 RX_DV_B/MII_MODE_B
23 TPRDM_A 63 RX_CLK_B
24 TPRDP_A 64 IOGND3
25 CDGND1 65 IOVDD3
26 TPTDM_A 66 MDIO
27 TPTDP_A 67 MDC
28 PFBIN2 68 CLK2MAC
29 ANAGND2 69 X2
30 ANA33VDD 70 X1
31 PFBOUT 71 RESET_N
32 RBIAS 72 TCK
33 ANAGND3 73 TDO
34 PFBIN3 74 TMS
35 TPTDP_B 75 TRSTN
36 TPTDM_B 76 TDI
37 CDGND2 77 IOGND4
38 TPRDP_B 78 IOVDD4
39 TPRDM_B 79 RX_CLK_A
40 ANAGND4 80 RX_DV_A/MII_MODE_A

3.2 Signal Descriptions

3.2.1 Serial Management Interface

SIGNAL NAME TYPE PIN NO. DESCRIPTION
MDC I 67 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.
MDIO I/O 66 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5-kΩ pullup resistor.

3.2.2 Clock Interface

SIGNAL NAME TYPE PIN NO. DESCRIPTION
X1 I 70 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83849I and must be connected to a 25 MHz 0.005% (+50 ppm) clock source. The DP83849I supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50-MHz
0.005% (+50 ppm) CMOS-level oscillator source.
X2 O 69 CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used.
CLK2MAC O 68 CLOCK TO MAC:
In MII mode, this pin provides a 25-MHz clock output to the system.
In RMII mode, this pin provides a 50-MHz clock output to the system.
This allows other devices to use the reference clock from the DP83849I without requiring additional clock sources.
If the system does not require the CLK2MAC signal, the CLK2MAC output must be disabled through the CLK2MAC disable strap.

3.2.3 MAC Data Interface

SIGNAL NAME TYPE PIN NO. DESCRIPTION
TX_CLK_A O 12 MII TRANSMIT CLOCK: 25-MHz Transmit clock output in 100-Mb/s mode or 2.5 MHz in 10-Mb/s mode derived from the 25-MHz reference clock.
TX_CLK_B 50
Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive.
SNI TRANSMIT CLOCK: 10-MHz Transmit clock output in 10-Mb/s SNI mode. The MAC must source TX_EN and TXD_0 using this clock.
TX_EN_A I 13 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0].
TX_EN_B 49
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: 10-MHz Transmit clock output in 10-Mb/s SNI mode. The MAC must source TX_EN and TXD_0 using this clock.
TXD[3:0]_A I 17, 16, 15, 14 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
TXD[3:0]_B 45, 46, 47, 48
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50-MHz reference clock.
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI mode).
RX_CLK_A O 79 MII RECEIVE CLOCK: Provides the 25-MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
RX_CLK_B 63 Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz reference for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10-MHz recovered receive clocks for 10 Mb/s SNI mode.
RX_DV_A O 80 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0].
RX_DV_B 62 RMII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[1:0]. This signal is not required in RMII mode, because CRS_DV includes the RX_DV signal, but is provided to allow simpler recovery of the Receive data.
This pin is not used in SNI mode.
RX_ER_A O 2 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode.
RX_ER_B 60 RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s mode. This pin is also asserted on detection of a False Carrier event. This pin is not required to be used by a MAC in RMII mode, because the Phy is required to corrupt data on a receive error.
This pin is not used in SNI mode.
RXD[3:0]_A O 9, 8, 5, 4 MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.
RXD[3:0]_B 53, 56, 57, 58 RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.
CRS_A/CRS_DV_A O 1 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
CRS_B/CRS_DV_B 61 RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see Section 4.6.
SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid receive data on the RXD_0 signal.
COL_A O 3 MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.
COL_B 59 While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision.
SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s SNI mode.

3.2.4 LED Interface

The DP83849I supports three configurable LED pins. The LEDs support two operational modes that are selected by the LED mode strap and a third operational mode that is register configurable. The definitions for the LEDs for each mode are detailed in the following table. Because the LEDs are also used as strap options, the polarity of the LED output is dependent on whether the pin is pulled up or down.

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SIGNAL NAME TYPE PIN NO. DESCRIPTION
LED_LINK_A I/O 19 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good.
LED_LINK_B 43
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.
LED_SPEED_A I/O 20 SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10 Mb/s. Functionality of this LED is independent of mode selected.
LED_SPEED_B 42
LED_ACT/LED_COL_A I/O 21 ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive.
LED_ACT/LED_COL_B 41
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision.

3.2.5 JTAG Interface

SIGNAL NAME TYPE PIN NO. DESCRIPTION
TCK I, PU 72 TEST CLOCK: This pin has a weak internal pullup.
TDO O 73 TEST OUTPUT:
TMS I, PU 74 TEST MODE SELECT: This pin has a weak internal pullup.
TRSTN I, PU 75 TEST RESET Active low test reset. This pin has a weak internal pullup.
TDI I, PU 76 TEST DATA INPUT: This pin has a weak internal pullup.

3.2.6 Reset and Power Down

SIGNAL NAME TYPE PIN NO. DESCRIPTION
RESET_N I, PU 71 RESET: Active Low input that initializes or re-initializes the DP83849I. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block section. All strap options are re-initialized as well.
PWRDOWN_INT_A I, PU 18 The default function of this pin is POWER DOWN.
PWRDOWN_INT_B 44
POWER DOWN: The pin is an active low input in this mode and must be asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. Although the pin has a weak internal pullup, some applications may require an external pullup resister. Register access is required for the pin to be used as an interrupt mechanism. See Section 6.2.4.2 for more details on the interrupt mechanisms.

3.2.7 Strap Options

The DP83849I uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2-kΩ resistor must be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pull down resistors. Because these pins may have alternate functions after reset is deasserted, they must not be connected directly to VCC or GND.

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SIGNAL NAME TYPE PIN NO. DESCRIPTION
PHYAD1 (RXD0_A) S, O, PD 4 PHY ADDRESS [4:1]: The DP83849I provides four PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset. Phy Address[0] selects between ports A and B.
PHYAD2 (RXD1_A) 5
PHYAD3 (RXD0_B) 58 The DP83849I supports PHY Address strapping for Port A even values 0 (<0000_0>) through 30 (<1111_0>). Port B will be strapped to odd
values 1 (<0000_1>) through 31 (<1111_1>).
PHYAD4 (RXD1_B) 57
PHYAD[4:1] pins have weak internal pulldown resistors.

AN_EN
(LED_ACT/LED_COL_A)

S, O, PU 21 Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins.

AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83849I according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2-kΩ resistors. These pins must NEVER be connected directly to GND or VCC.

The value set at this input is latched into the DP83849I at Hardware-Reset.

The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.

The default is 111 because these pins have internal pullups.
AN1_A (LED_SPEED_A) 20
AN0_A (LED_LINK_A) 19
AN_EN
(LED_ACT/LED_COL_B)		 41
AN1_B (LED_SPEED_B) 42
AN0_B (LED_LINK_B) 43
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T, Half-Duplex
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
MII_MODE_A (RX_DV_A) S, O, PD 80 MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pullups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes of operation, determined by the status of the SNI_MODE strap. Because the pins include internal pulldowns, the default values are 0. Both MAC Data Interfaces must have their RMII Mode settings the same; that is, both in RMII mode or both not in RMII mode

The following table details the configurations:
SNI_MODE_A (TXD3_A) 17
MII_MODE_B (RX_DV_B) 62
SNI_MODE_B (TXD3_B) 45
MII_MODE SNI_MODE MAC Interface Mode
0 X MII Mode
1 0 RMII Mode
1 1 10-Mb/s SNI mode
LED_CFG_A
(CRS_A/CRS_DV_A) 		S, O, PU 1 LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled through the strap option. All modes are configurable through register access.

See Table 5-2 for LED Mode Selection.
LED_CFG_B
(CRS_B/CRS_DV_B)		 61
MDIX_EN_A (RX_ER_A) S, O, PU 2 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pulldown will disable AutoMDIX mode.
MDIX_EN_B (RX_ER_B) 60
ED_EN_A (RXD3_A) S, O, PD 9 Energy Detect ENABLE: Default is to disable Energy Detect mode. This strapping option enables Energy Detect mode for the port. In Energy Detect mode, the device will initially be in a low-power state until detecting activity on the wire. An external pullup will enable Energy Detect mode.
ED_EN_B (RXD3_B) 53
CLK2MAC_DIS (RXD2_A) S, O, PD 8 Clock to MAC Disable: This strapping option disables (floats) the CLK2MAC pin. Default is to enable CLK2MAC output. An external pullup will disable (float) the CLK2MAC pin. If the system does not require the CLK2MAC signal, the CLK2MAC output must be disabled through this strap option.
EXTENDER_EN (RXD2_B) S, O, PD 56 Extender Mode Enable: This strapping option enables Extender Mode for both ports. When enabled, the strap will enable Single Clock MII TX and RX modes unless RMII Mode is also strapped. SNI Mode cannot be strapped if Extender Mode is strapped.

3.2.8 PMD Interface for 10 Mb/s and 100 Mb/s

SIGNAL NAME TYPE PIN NO. DESCRIPTION
TPTDM_A I/O 26 10BASE-T or 100BASE-TX Transmit Data

In 10BASE-T or 100BASE-TX: Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.

These pins require 3.3-V bias for operation.
TPTDP_A 27
TPTDM_B 36
TPTDP_B 35
TPRDM_A I/O 23 10BASE-T or 100BASE-TX Receive Data

In 10BASE-T or 100BASE-TX: Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.

These pins require 3.3-V bias for operation.
TPRDP_A 24
TPRDM_B 39
TPRDP_B 38

3.2.9 Special Connections

SIGNAL NAME TYPE PIN NO. DESCRIPTION
RBIAS I 32 Bias Resistor Connection: A 4-87 kΩ 1% resistor must be connected from RBIAS to GND.
PFBOUT O 31 Power Feedback Output: Parallel caps, 10 µF and 0.1 µF, must be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 13), PFBIN2 (pin 27), PFBIN3 (pin 35), PFBIN4 (pin 49). See Section 6.2.3 for proper placement pin.
PFBIN1 I 7 Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 µF must be connected close to each pin.

Note: Do not supply power to these pins other than from PFBOUT.

PFBIN2 28
PFBIN3 34
PFBIN4 54

3.2.10 Power Supply Pins

SIGNAL NAME PIN NO. DESCRIPTION
IOVDD1, IOVDD2, IOVDD3, IOVDD4 11, 51, 65, 78 I/O 3.3-V Supply
IOGND1, IOGND2, IOGND3, IOGND4 10, 52, 64, 77 I/O Ground
COREGND1, COREGND2 6, 55 Core Ground
CDGND1, CDGND2 25, 37 CD Ground
ANA33VDD 30 Analog 3.3-V Supply
ANAGND1, ANAGND2, ANAGND3, ANAGND4 22, 29, 33, 40 Analog Ground