SNLS654B April   2021  – January 2023 DP83TC812R-Q1 , DP83TC812S-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Diagnostic Tool Kit
        1. 8.3.1.1 Signal Quality Indicator
        2. 8.3.1.2 Electrostatic Discharge Sensing
        3. 8.3.1.3 Time Domain Reflectometry
        4. 8.3.1.4 Voltage Sensing
        5. 8.3.1.5 BIST and Loopback Modes
          1. 8.3.1.5.1 Data Generator and Checker
          2. 8.3.1.5.2 xMII Loopback
          3. 8.3.1.5.3 PCS Loopback
          4. 8.3.1.5.4 Digital Loopback
          5. 8.3.1.5.5 Analog Loopback
          6. 8.3.1.5.6 Reverse Loopback
      2. 8.3.2 Compliance Test Modes
        1. 8.3.2.1 Test Mode 1
        2. 8.3.2.2 Test Mode 2
        3. 8.3.2.3 Test Mode 4
        4. 8.3.2.4 Test Mode 5
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Down
      2. 8.4.2  Reset
      3. 8.4.3  Standby
      4. 8.4.4  Normal
      5. 8.4.5  Sleep Ack
      6. 8.4.6  Sleep Request
      7. 8.4.7  Sleep Fail
      8. 8.4.8  Sleep
      9. 8.4.9  Wake-Up
      10. 8.4.10 TC10 System Example
      11. 8.4.11 Media Dependent Interface
        1. 8.4.11.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 8.4.11.2 Auto-Polarity Detection and Correction
        3. 8.4.11.3 Jabber Detection
        4. 8.4.11.4 Interleave Detection
      12. 8.4.12 MAC Interfaces
        1. 8.4.12.1 Media Independent Interface
        2. 8.4.12.2 Reduced Media Independent Interface
        3. 8.4.12.3 Reduced Gigabit Media Independent Interface
        4. 8.4.12.4 Serial Gigabit Media Independent Interface
      13. 8.4.13 Serial Management Interface
      14. 8.4.14 Direct Register Access
      15. 8.4.15 Extended Register Space Access
      16. 8.4.16 Write Address Operation
        1. 8.4.16.1 MMD1 - Write Address Operation
      17. 8.4.17 Read Address Operation
        1. 8.4.17.1 MMD1 - Read Address Operation
      18. 8.4.18 Write Operation (No Post Increment)
        1. 8.4.18.1 MMD1 - Write Operation (No Post Increment)
      19. 8.4.19 Read Operation (No Post Increment)
        1. 8.4.19.1 MMD1 - Read Operation (No Post Increment)
      20. 8.4.20 Write Operation (Post Increment)
        1. 8.4.20.1 MMD1 - Write Operation (Post Increment)
      21. 8.4.21 Read Operation (Post Increment)
        1. 8.4.21.1 MMD1 - Read Operation (Post Increment)
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Register Access Summary
      2. 8.6.2 DP83TC812 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information Disclaimer
    2. 9.2 Application Information
    3. 9.3 Typical Applications
      1. 9.3.1 Design Requirements
        1. 9.3.1.1 Physical Medium Attachment
          1. 9.3.1.1.1 Common-Mode Choke Recommendations
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Metal Pour
      4. 11.1.4 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.10 TC10 System Example

The following block diagrams explains how TC10 sleep and wake function works in a system.
Figure 8-12 TC10 System Example - Remote Wake
Figure 8-13 TC10 System Example - Local Wake

Remote Wake Up

For remote wake up, the initial state of the system is TC10 sleep. Core voltages to the PHY and MAC are turned off but the VSLEEP of the PHY is present. At some time, wake-up pulses (WUP) are received on the MDI lines. The PHY recevies the message and if its a valid sequence then the PHY wakes up and drives INH pin HIGH. INH pin is used as enable input to voltage regulator (e.g. LDO). Voltage regulators turns on and supplies power to a power management device. The power management device then supplies power to the PHY, MAC, and any other devices on the system. The whole system powers up and becomes operational.

Wake Forwarding

DP83TC812-Q1

support wake forwarding feature. When the device received Wake-Up Requests (WUR) or Wake-Up Pulses (MDI) on the MDI then the PHY will transmit an 40µs high pulse on the WAKE pin. This can be used to wake-up any other PHYs on the system that are in TC-10 sleep.

Local Wake Up

For local wake, it is assumed that some portion of the system is already active and the PHY is in TC10 sleep. As a example, the system might have micro-controller in active mode to control the WAKE pin of the PHY. When the MCU wants to wake up the PHY from TC10 sleep, it raises the WAKE pin to 3.3V to send a wake pulse (min. 40μs). The PHY wakes up and drives INH pin HIGH. INH pin is used as enable input to voltage regulator (e.g. LDO). Voltage regulators turns on and supplies power to a power management device. The power management device then supplies power to the PHY. Any other device on the system that depends on the PHY wake up can now be powered up and the system becomes operational.

Local Sleep

When the PHY is in normal operational mode and the MAC needs to put it in TC10 sleep, it initiates the TC10 sleep process via SMI on the PHY. DP83TC812-Q1 then sends LPS signals on MDI to the link partner. If the link partner also agrees to enter TC10 sleep, the host PHY enters TC10 sleep. It then releases the INH pin and it gets pulled low through the external pull down resistor. Voltage regulator that uses INH pin as enable input will be turned off. PHY, MAC, and any other devices that are dependent on the voltage regulator will be turned off. The PHY will still have VSLEEP voltage present and continue to stay in TC10 sleep.