SPRSP35K February   2019  – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
        2. 5.3.3.2 WKUP Domain
      4. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 MCU Domain
        3. 5.3.4.3 WKUP Domain
      5. 5.3.5  I3C
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
        2. 5.3.6.2 MCU Domain
      7. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
        2. 5.3.7.2 MCU Domain
      8. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
        2. 5.3.8.2 MCU Domain
        3. 5.3.8.3 WKUP Domain
      9. 5.3.9  MDIO
        1. 5.3.9.1 MCU Domain
      10. 5.3.10 CPSW2G
        1. 5.3.10.1 MCU Domain
      11. 5.3.11 CPSW9G
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 ECAP
        1. 5.3.12.1 MAIN Domain
      13. 5.3.13 EQEP
        1. 5.3.13.1 MAIN Domain
      14. 5.3.14 EHRPWM
        1. 5.3.14.1 MAIN Domain
      15. 5.3.15 USB
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 SERDES
        1. 5.3.16.1 MAIN Domain
      17. 5.3.17 OSPI
        1. 5.3.17.1 MCU Domain
      18. 5.3.18 Hyperbus
        1. 5.3.18.1 MCU Domain
      19. 5.3.19 GPMC
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 MMC
        1. 5.3.20.1 MAIN Domain
      21. 5.3.21 CPTS
        1. 5.3.21.1 MCU Domain
        2. 5.3.21.2 MAIN Domain
      22. 5.3.22 UFS
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 PRU_ICSSG [Currently Not Supported]
        1. 5.3.23.1 MAIN Domain
      24. 5.3.24 MCASP
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 DP
        1. 5.3.26.1 MAIN Domain
      27. 5.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 5.3.27.1 MAIN Domain
      28. 5.3.28 DSI_TX
        1. 5.3.28.1 MAIN Domain
      29. 5.3.29 VPFE
        1. 5.3.29.1 MAIN Domain
      30. 5.3.30 DMTIMER
        1. 5.3.30.1 MAIN Domain
        2. 5.3.30.2 MCU Domain
      31. 5.3.31 Emulation and Debug
        1. 5.3.31.1 MAIN Domain
      32. 5.3.32 System and Miscellaneous
        1. 5.3.32.1 Boot Mode Configuration
          1. 5.3.32.1.1 MAIN Domain
          2. 5.3.32.1.2 MCU Domain
        2. 5.3.32.2 Clock
          1. 5.3.32.2.1 MAIN Domain
          2. 5.3.32.2.2 WKUP Domain
        3. 5.3.32.3 System
          1. 5.3.32.3.1 MAIN Domain
          2. 5.3.32.3.2 WKUP Domain
        4. 5.3.32.4 EFUSE
      33. 5.3.33 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On-Hour (POH) Limits
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
    6. 6.6 Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI-2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  MLB LVCMOS Electrical Characteristics
      9. 6.6.9  LVCMOS Electrical Characteristics
      10. 6.6.10 USB2PHY Electrical Characteristics
      11. 6.6.11 SerDes 4-L-PHY/2-L-PHY Electrical Characteristics
      12. 6.6.12 UFS M-PHY Electrical Characteristics
      13. 6.6.13 eDP/DP AUX-PHY Electrical Characteristics
      14. 6.6.14 DDR0 Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALF Package
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.9.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
        6. 6.9.2.6 Entry and Exit of MCU Only State
        7. 6.9.2.7 Entry and Exit of DDR Retention State
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input and Output Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.1.1 Load Capacitance
            2. 6.9.4.1.1.2 Shunt Capacitance
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.9.4.1.3.1 Load Capacitance
            2. 6.9.4.1.3.2 Shunt Capacitance
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.6.1 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Module and Peripheral Clocks Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  ATL
          1. 6.9.5.1.1 ATL_PCLK Timing Requirements
          2. 6.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.9.5.2  VPFE
        3. 6.9.5.3  CPSW2G
          1. 6.9.5.3.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.3.2 CPSW2G RMII Timings
            1. 6.9.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.9.5.3.3 CPSW2G RGMII Timings
            1. 6.9.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.9.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 6.9.5.4  CPSW9G
          1. 6.9.5.4.1 CPSW9G MDIO Interface Timings
          2. 6.9.5.4.2 CPSW9G RMII Timings
            1. 6.9.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 6.9.5.4.3 CPSW9G RGMII Timings
            1. 6.9.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 6.9.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 6.9.5.5  CSI-2
        6. 6.9.5.6  DDRSS
        7. 6.9.5.7  DSS
        8. 6.9.5.8  eCAP
          1. 6.9.5.8.1 Timing Requirements for eCAP
          2. 6.9.5.8.2 Switching Characteristics for eCAP
        9. 6.9.5.9  EPWM
          1. 6.9.5.9.1 Timing Requirements for eHRPWM
          2. 6.9.5.9.2 Switching Characteristics for eHRPWM
        10. 6.9.5.10 eQEP
          1. 6.9.5.10.1 Timing Requirements for eQEP
          2. 6.9.5.10.2 Switching Characteristics for eQEP
        11. 6.9.5.11 GPIO
          1. 6.9.5.11.1 GPIO Timing Requirements
          2. 6.9.5.11.2 GPIO Switching Characteristics
        12. 6.9.5.12 GPMC
          1. 6.9.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.9.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.9.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.9.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.9.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.9.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.9.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.9.5.12.4 GPMC0 IOSET
        13. 6.9.5.13 HyperBus
          1. 6.9.5.13.1 Timing Requirements for HyperBus
          2. 6.9.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 6.9.5.14 I2C
        15. 6.9.5.15 I3C
        16. 6.9.5.16 MCAN
        17. 6.9.5.17 MCASP
        18. 6.9.5.18 MCSPI
          1. 6.9.5.18.1 MCSPI — Master Mode
          2. 6.9.5.18.2 MCSPI — Slave Mode
        19. 6.9.5.19 MMCSD
          1. 6.9.5.19.1 MMC0 - eMMC Interface
            1. 6.9.5.19.1.1 Legacy SDR Mode
            2. 6.9.5.19.1.2 High Speed SDR Mode
            3. 6.9.5.19.1.3 High Speed DDR Mode
            4. 6.9.5.19.1.4 HS200 Mode
          2. 6.9.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 6.9.5.19.2.1 Default Speed Mode
            2. 6.9.5.19.2.2 High Speed Mode
            3. 6.9.5.19.2.3 UHS–I SDR12 Mode
            4. 6.9.5.19.2.4 UHS–I SDR25 Mode
            5. 6.9.5.19.2.5 UHS–I SDR50 Mode
            6. 6.9.5.19.2.6 UHS–I DDR50 Mode
            7. 6.9.5.19.2.7 UHS–I SDR104 Mode
        20. 6.9.5.20 CPTS
          1. 6.9.5.20.1 CPTS Timing Requirements
          2. 6.9.5.20.2 CPTS Switching Characteristics
        21. 6.9.5.21 OSPI
          1. 6.9.5.21.1 OSPI PHY Mode
            1. 6.9.5.21.1.1 OSPI With Data Training
              1. 6.9.5.21.1.1.1 OSPI Switching Characteristics – Data Training
            2. 6.9.5.21.1.2 OSPI Without Data Training
              1. 6.9.5.21.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.9.5.21.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.9.5.21.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.9.5.21.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 6.9.5.21.2 OSPI Tap Mode
            1. 6.9.5.21.2.1 OSPI Tap SDR Timing
            2. 6.9.5.21.2.2 OSPI Tap DDR Timing
        22. 6.9.5.22 PCIE
        23. 6.9.5.23 Timers
          1. 6.9.5.23.1 Timing Requirements for Timers
          2. 6.9.5.23.2 Switching Characteristics for Timers
        24. 6.9.5.24 UART
          1. 6.9.5.24.1 Timing Requirements for UART
          2. 6.9.5.24.2 UART Switching Characteristics
        25. 6.9.5.25 USB
      6. 6.9.6 Emulation and Debug
        1. 6.9.6.1 Trace
        2. 6.9.6.2 JTAG
          1. 6.9.6.2.1 JTAG Electrical Data and Timing
            1. 6.9.6.2.1.1 JTAG Timing Requirements
            2. 6.9.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
      3. 7.2.3 DSP C71x
      4. 7.2.4 DSP C66x
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 GPU
      2. 7.3.2 D5520MP2
      3. 7.3.3 VXE384MP2
    4. 7.4 Other Subsystems
      1. 7.4.1 MSMC
      2. 7.4.2 NAVSS
        1. 7.4.2.1 NAVSS0
        2. 7.4.2.2 MCU_NAVSS
      3. 7.4.3 PDMA Controller
      4. 7.4.4 Power Supply
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  ATL
        3. 7.4.5.3  CSI
          1. 7.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.4.5.4  CPSW2G
        5. 7.4.5.5  CPSW9G
        6. 7.4.5.6  DCC
        7. 7.4.5.7  DDRSS
        8. 7.4.5.8  DSS
          1. 7.4.5.8.1 DSI
          2. 7.4.5.8.2 eDP
        9. 7.4.5.9  VPFE
        10. 7.4.5.10 eCAP
        11. 7.4.5.11 EPWM
        12. 7.4.5.12 ELM
        13. 7.4.5.13 ESM
        14. 7.4.5.14 eQEP
        15. 7.4.5.15 GPIO
        16. 7.4.5.16 GPMC
        17. 7.4.5.17 Hyperbus
        18. 7.4.5.18 I2C
        19. 7.4.5.19 I3C
        20. 7.4.5.20 MCAN
        21. 7.4.5.21 MCASP
        22. 7.4.5.22 MCRC Controller
        23. 7.4.5.23 MCSPI
        24. 7.4.5.24 MMC/SD
        25. 7.4.5.25 OSPI
        26. 7.4.5.26 PCIE
        27. 7.4.5.27 SerDes
        28. 7.4.5.28 WWDT
        29. 7.4.5.29 Timers
        30. 7.4.5.30 UART
        31. 7.4.5.31 USB
        32. 7.4.5.32 UFS
  9. 8 Applications and Implementation
    1. 8.1 Power Supply Mapping
    2. 8.2 Device Connection and Layout Fundamentals
      1. 8.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.2.1.1 Power Distribution Network Implementation Guidance
      2. 8.2.2 External Oscillator
      3. 8.2.3 JTAG and EMU
      4. 8.2.4 Reset
      5. 8.2.5 Unused Pins
      6. 8.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 8.3 Peripheral- and Interface-Specific Design Information
      1. 8.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.3.2.1 No Loopback and Internal Pad Loopback
        2. 8.3.2.2 External Board Loopback
        3. 8.3.2.3 DQS (only available in Octal Flash devices)
      3. 8.3.3 SERDES REFCLK Design Guidelines
      4. 8.3.4 USB VBUS Design Guidelines
      5. 8.3.5 System Power Supply Monitor Design Guidelines
      6. 8.3.6 High Speed Differential Signal Routing Guidance
      7. 8.3.7 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALF|827
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Revision History

Changes from August 28, 2021 to April 22, 2024 (from Revision J (August 2021) to Revision K (April 2024))

  • Global:: Updated document titleGo
  • Global: Added Silicon Revision 2.0 (SR2.0) device-specific info throughout the documentGo
  • Global:: Moved the Revision History section to the back of the documentGo
  • Global:: Deleted all OLDI/LVDS content; n/a to this device suiteGo
  • Global:: Deleted the "Power Consumption Summary" section (was after Section 6.5, Operating Performance Points)Go
  • (Features): Updated/Changed the Integrated Ethernet switch bullets and sub-bulletsGo
  • (Features): Updated/Changed the Functional Safety bullets to include the received Functional Safety-Compliant certificationGo
  • (Description): Updated the lead-in sentenceGo
  • (Package Information): Updated/Changed the "Device Information" table to "Package Information" table and revamped table content to new formatGo
  • (Functional Block Diagram): Added SDK software build sheet NoteGo
  • (Device Comparison): Updated/Changed the MSMC capacity for DRA829VM to "8MB". Now both DRA829JM and DRA829VM devices are "8MB (On-Chip SRAM with ECC)"Go
  • (Device Comparison): Moved the "Security Accelerators" row to be group sequenced with the other accelerator rows and to match other device comparison tables within this device suiteGo
  • (Device Comparison): Added SDK software build sheet NoteGo
  • (Pin Attributes): Added the secondary pin multiplexing functions for the DSI and controlled by CTRLMMR regsGo
  • (Pin Attributes): Added the secondary pin multiplexing functions for the MCU_ADC and controlled by CTRLMMR regsGo
  • (Pin Attributes): Added "The MUXMODE field is not used to select …" footnote for the WKUP_GPIO0_[68:83] signals in the Pin Attributes tableGo
  • (Pin Attributes): Added reset states to the BALL RESET STATE column for mmc0_* pins in the Pin Attributes tableGo
  • (WKUP Domain GPIO0 Signal Descriptions): Added missing WKUP_GPIO0_[68:83] signalsGo
  • (Power Supply Signal Description): Added "±10%" to the "This pin must always be … capacitor to VSS" footnoteGo
  • (Connections for Unused Pins): Added the "VMON_ER_VSYS" (M26) and "VMON_IR_VEXT" (V19) signals to the "Each of these balls must be connected to VSS .." CONNECTIONS REQUIREMENT descriptionGo
  • (Connections for Unused Pins): Updated/Changed "All VMON and power balls must be …" Note deleting "VMON and"Go
  • (Pin Connectivity Requirements): Updated/Changed the section title (was "Connections for Unused Pins")Go
  • (Connectivity Requirements (ALF Package)): Updated/Changed the table title (was "Unused Balls Specific Connection Requirements")Go
  • (Pin Connectivity Requirements): Added "as a boot source" to the Note specifying MMC1_SDCD and MMC2_SDCD should be pulled down to work properlyGo
  • (Absolute Maximum Ratings): Moved "VMON_IR_VEXT" and "VMON_ER_VSYS"signals from "Steady State Max. Voltage at all other IO pins" to "Steady State Max. Voltage at all fail-safe IO pins"Go
  • Added the "VMON_IR_VEXT" and "VMON_ER_VSYS"signals to the "Fail-safe IO terminals are designed …" paragraphGo
  • (Absolute Maximum Ratings): Updated/Changed "JESD78D (Class II)" to " JESD78E (Class II)" in the "For current pulse injection: .." footnoteGo
  • Updated/Changed the UNIT specified for the Latch-Up Performance MAX parameter from "mV" to "V"Go
  • (ESD Ratings): Added the AEC - Q100 document revision letter to both HBM and CDM rowsGo
  • (Recommended Operating Conditions): Deleted the "Refer to Power-On-Hour (POH) Limits for limitations." footnote and associated cross-referenceGo
  • (I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics): Updated/Changed the VOL, Output low-level voltage MAX value under the 3.3-V MODE from "0.4 × VDDSHV" to "0.4" VGo
  • (I2C OD FS Electrical Characteristics): Added a footnote to explain the IOL parameterGo
  • (I2C OD FS Electrical Characteristics): Defined MAX VIH values for 1.8-V mode and 3.3-V mode and included a footnote that describes how these values are also defined in the absolute maximum input voltageGo
  • (I2C OD FS Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to describe the SRI parameter for 1.8-V MODEGo
  • (I2C OD FS Electrical Characteristics): Added both the MIN and MAX input slew rate value and added associated footnotes to describe the SRI parameter for 3.3-V MODEGo
  • (I2C OD FS Electrical Characteristics): Added associated "I2C Hs-mode is not supported …" footnote to the 3.3-V MODE table sectionGo
  • (I2C OD FS Electrical Characteristics): Added associated "The IOL parameter defines …" footnote to the IOL, low level output current parameter for both 1.8-V MODE and 3.3-V MODEGo
  • (SDIO Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to describe the SRI parameter for 1.8-V MODEGo
  • (SDIO Electrical Characteristics): Added both the MIN and MAX input slew rate value and added associated footnotes to describe the SRI parameter for 3.3-V MODEGo
  • (CSI-2/DSI D-PHY Electrical Characteristics): Updated the section titleGo
  • (CSI-2/DSI D-PHY Electrical Characteristics): Deleted the Electrical Characteristics table and added a Note for the CSI-2/DSI D-PHY interfaces electrical characteristics compliance with MIPI D-PHY specifications v1.2 dated August 1, 2014Go
  • (LVCMOS Electrical Characteristics): Added a footnote to explain the IOL and IOH parametersGo
  • (LVCMOS Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to describe the SRI parameter for 1.8-V MODEGo
  • (LVCMOS Electrical Characteristics): Added both the MIN and MAX input slew rate value and added associated footnotes to describe the SRI parameter for 3.3-V MODEGo
  • (LVCMOS Electrical Characteristics): Defined the minimum input slew rate value and added notes to describe this parameterGo
  • (SerDes 4-L-PHY/2-L-PHY Electrical Characteristics): Updated/Changed the section titleGo
  • (2-L-PHY SERDES REFCLK Electrical Characteristics): Added missing tableGo
  • (UFS M-PHY Electrical Characteristics): Added missing section titleGo
  • (eDP/DP AUX-PHY Electrical Characteristics): Added missing section titleGo
  • (WKUP_OSC0 Switching Characteristics – Crystal Mode): Updated/Changed CXIXO, XI to XO Mutual Capacitance MAX value from "0.9fF" to "0.1pF"Go
  • (WKUP_LFOSC0 Internal Oscillator Clock Source): Updated/Changed the ESR row UNIT column from "Ω" to "kΩ" in the WKUP_LFOSC0 Crystal Electrical Characteristics tableGo
  • (LFXOSC Modes of Operation table): Updated/Changed the value of PD_C for BYPASS mode from "X" to "0"Go
  • (DDRSS): Added a bullet below the JEDEC JESD209-4B standard compliant LPDDR4 SDRAM devices features currently supported bulletsGo
  • (GPIO): Updated/Changed the GPIO Timings Conditions table and associated footnoteGo
  • (GPIO Timing Requirements): Updated/Changed the GPIO Timings Requirements tableGo
  • (GPIO Switching Characteristics): Updated/Changed the GPIO Switching Characteristics tableGo
  • (MMC1/2 - SD/SDIO Interface): Updated/Changed the "OTAPDLYENA, DELAY ENABLE" and "OTAPDLYSEL, DELAY VALUE" for the Default Speed and High Speed modes from "0x0" to "0x1"Go
  • (OSPI DLL Delay Mapping - DDR Timing Modes): Updated/Changed the DELAY VALUES for both OSPI0 and OSPI1 and re-worked the Table formatting viewGo
  • (OSPI Tap Mode): Added new sectionGo
  • (OSPI Timing Requirements – Tap SDR Mode): Added new sectionGo
  • (OSPI Timing Requirements – Tap DDR Mode): Added new sectionGo
  • (Nomenclature Description): Added "C" value to the "r, Device revision" row to represent SR 2.0 partsGo
  • (Device Naming Convention): Added content to the "Base production part number" Values plus Description and "Device Type" Description columns of the Nomenclature Description tableGo
  • (Tools and Software/Development Tools): Deleted the Clock Tree Tool reference and contentGo
  • (Documentation Support): Updated/Changed the document titles for both the TRM and Errata to include Silicon Revisions 2.0, 1.1, and still 1.0Go