SLVSCV1E September   2015  – February 2017 DRV3205-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Serial Peripheral Interface Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Programming
      1. 7.3.1 SPI
        1. Address Mode Transfer
          1. SPI Address Transfer Phase
        2. SPI Data Transfer Phase
        3. Device Data Response
    4. 7.4 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Three-Phase Motor Drive-Device for Automotive Application
    3. 8.3 System Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

Use the following guidelines when designing a PCB for the DRV3205-Q1:

  • In addition to the GND pins, the DRV3205-Q1 makes an electrical connection to GND through the PowerPAD. Always check that the PowerPAD has been properly soldered (see PowerPAD™ Thermally Enhanced Package [SLMA002]).
  • The VS bypass capacitors should be placed close to the power supply terminals. See the VS box in Figure 19
  • Place the VCC5 and VCC5 bypass capacitors close to the corresponding pins with a low impedance path to the ground plane pin (pin 16). See the VCC3 VCC5 bypass box in Figure 19.
  • AGND should all be tied to the ground plane through a low impedance trace or copper fill.
  • Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
  • Try to clear the space around and below the DRV3205-Q1 to allow for better heat spreading from the PowerPAD.
  • Route the sense lines, IPx and INx, each with a unique trace, directly to either side of the sense resistor. See the SENSE box in Figure 19.
  • Keep the BOOST components close to the device and current loops small. See the BOOST boxes in Figure 19.
  • Place the current sense resistors close to the respective low-side FET. See the SENSE box in Figure 19.
  • Place the GNDLS_B resistor close to the device pin. See the GNDLS_B box in Figure 19.

Layout Example

DRV3205-Q1 layout_example_slvscv1.gif Figure 19. Layout Schematic