SBOS814 December   2016 DRV401-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Magnetic Probe (Sensor) Interface
      2. 7.3.2  PWM Processing
      3. 7.3.3  Compensation Driver
      4. 7.3.4  External Compensation Coil Driver
      5. 7.3.5  Shunt Sense Amplifier
      6. 7.3.6  Over-Range Comparator
      7. 7.3.7  Voltage Reference
      8. 7.3.8  Demagnetization
      9. 7.3.9  Power-On and Brownout
      10. 7.3.10 Error Conditions
      11. 7.3.11 Protection Recommendations
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Functional Principle of Closed-Loop Current Sensors with Magnetic Probe Using the DRV401-Q1 Device
      2. 8.1.2 Basic Connection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH® Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Thermal Pad

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

12.1 Thermal Pad

Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but board layout greatly influences overall heat dissipation. Table 1 shows the thermal resistance (θJA) for the package with the exposed thermal pad soldered to a normal PCB, as described in PowerPAD Thermally-Enhanced Package (SLMA002). Refer to EIA/JEDEC Specifications JESD51-0 to 7, QFN/SON PCB Attachment (SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017). These documents are available for download at www.ti.com.

Table 1. θJA and θJP Estimations According to EIA/JED51-7(1)

PARAMETER VQFN
θJP 9
θJA with still air 40
θJA with forced airflow (150 lfm) 38
(1) θJA = junction-to-ambient thermal resistance.
(2) θJP = junction-to-pad thermal resistance

TI recommends measuring the temperature as close as possible to the thermal pad. The relatively low thermal impedance, θJP, of less than 10°C/W (with some additional °C/W to the temperature test point on the PCB) allows good estimation of the junction temperature in the application.

The thermal pad on the PCB must contain nine or more vias for the VQFN package.

Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load conditions must be tested in the actual operating environment to ensure proper thermal conditions. Minimize thermal stress for proper long-term operation with a junction temperature well below 125°C.

NOTE

All thermal models have an accuracy ≈ 20%.