SLVSFY9B June   2021  – August 2021 DRV8212

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics DSG Package
    7. 7.7 Typical Characteristics DRL Package
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Control Modes
        1. 8.3.2.1 PWM Control Mode (DSG: MODE = 0 and DRL)
        2. 8.3.2.2 PH/EN Control Mode (DSG: MODE = 1)
        3. 8.3.2.3 Half-Bridge Control Mode (DSG: MODE = Hi-Z)
      3. 8.3.3 Protection Circuits
        1. 8.3.3.1 Supply Undervoltage Lockout (UVLO)
        2. 8.3.3.2 OUTx Overcurrent Protection (OCP)
        3. 8.3.3.3 Thermal Shutdown (TSD)
      4. 8.3.4 Pin Diagrams
        1. 8.3.4.1 Logic-Level Inputs
        2. 8.3.4.2 Tri-Level Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Sleep Mode
      3. 8.4.3 Fault Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Full-Bridge Driving
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Supply Voltage
          2. 9.2.1.2.2 Control Interface
          3. 9.2.1.2.3 Low-Power Operation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Half-Bridge Driving
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Supply Voltage
          2. 9.2.2.2.2 Control Interface
          3. 9.2.2.2.3 Low-Power Operation
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Coil Relay Driving
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Supply Voltage
          2. 9.2.3.2.2 Control Interface
          3. 9.2.3.2.3 Low-Power Operation
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Current Sense
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Shunt Resistor Sizing
          2. 9.2.4.2.2 RC Filter
    3. 9.3 Current Capability and Thermal Performance
      1. 9.3.1 Power Dissipation and Output Current Capability
      2. 9.3.2 Thermal Performance
        1. 9.3.2.1 Steady-State Thermal Performance
        2. 9.3.2.2 Transient Thermal Performance
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.2 Thermal Performance

The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.

The data in this section was simulated using the following criteria:

WSON (DSG package)

  • 2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
    • Top layer: DRV8212 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8212. Bottom layer copper area varies with top copper area.
  • 4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
    • Top layer: DRV8212 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Mid layer 1: GND plane thermally connected to DRV8212 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm.
    • Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
    • Bottom layer: signal layer with small copper pad underneath DRV8212 and thermally connected through via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the package (2 mm x 2 mm). Bottom pad size remains constant as top copper plane is varied.

Figure 9-29 shows an example of the simulated board for the HTSSOP package. Table 9-7 shows the dimensions of the board that were varied for each simulation.

GUID-20201208-CA0I-WKBX-LK2B-8SX5VSFGVQVN-low.gif Figure 9-29 WSON PCB model top layer
Table 9-7 Dimension A for 16-pin PWP package
Cu area (mm2) Dimension A (mm)
2 15.11
4 20.98
8 29.27
16 40.99

SOT (DRL package)

  • 2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
    • Top layer: DRV8212 SOT package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Bottom layer: ground plane thermally connected through vias under the DRV8212DRL package footprint. Bottom layer copper area varies with top copper area.
  • 4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the DRV8212DRL package footprint (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
    • Top layer: DRV8212 SOT package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Mid layer 1: GND plane thermally connected under DRV8212DRL package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm.
    • Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
    • Bottom layer: signal layer with small copper pad underneath DRV8212DRL and thermally connected through via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the package (1.2 mm x 1.6 mm). Bottom pad size remains constant as top copper plane is varied.

Figure 9-30 shows an example of the simulated board for the HTSSOP package. Table 9-8 shows the dimensions of the board that were varied for each simulation.

Figure 9-30 SOT PCB model top layer
Table 9-8 Dimension A for 16-pin PWP package
Cu area (mm2) Dimension A (mm)
2 15.11
4 20.98
8 29.27
16 40.99