SLVSHO5 April   2024 DRV8215

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Operating Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Summary of Features
      3. 7.3.3 Bridge Control
      4. 7.3.4 Current Sense and Regulation (IPROPI)
        1. 7.3.4.1 Current Sensing and Current Mirror Gain Selection
        2. 7.3.4.2 Current Regulation
          1. 7.3.4.2.1 Fixed Off-Time Current Regulation
          2. 7.3.4.2.2 Cycle-By-Cycle Current Regulation
      5. 7.3.5 Stall Detection
      6. 7.3.6 Motor Voltage and Speed Regulation
        1. 7.3.6.1 Internal Bridge Control
        2. 7.3.6.2 Setting Speed/Voltage Regulation Parameters
          1. 7.3.6.2.1 Speed and Voltage Set
          2. 7.3.6.2.2 Speed Scaling Factor
            1. 7.3.6.2.2.1 Target Speed Setting Example
          3. 7.3.6.2.3 Motor Resistance Inverse
          4. 7.3.6.2.4 Motor Resistance Inverse Scale
          5. 7.3.6.2.5 KMC Scaling Factor
          6. 7.3.6.2.6 KMC
          7. 7.3.6.2.7 VSNS_SEL
        3. 7.3.6.3 Soft-Start and Soft-Stop
          1. 7.3.6.3.1 TINRUSH
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 Overcurrent Protection (OCP)
        2. 7.3.7.2 Thermal Shutdown (TSD)
        3. 7.3.7.3 VCC Undervoltage Lockout (UVLO)
        4. 7.3.7.4 Overvoltage Protection (OVP)
        5. 7.3.7.5 nFAULT Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Communication
        1. 7.5.1.1 I2C Write
        2. 7.5.1.2 I2C Read
  9. 8 Register Map
    1. 8.1 DRV8215_STATUS Registers
    2. 8.2 DRV8215_CONFIG Registers
    3. 8.3 DRV8215_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Brushed DC Motor
      1. 9.2.1 Design Requirements
      2. 9.2.2 Stall Detection
        1. 9.2.2.1 Application Description
          1. 9.2.2.1.1 Stall Detection Timing
          2. 9.2.2.1.2 Hardware Stall Threshold Selection
      3. 9.2.3 Motor Speed and Voltage Regulation Application
        1. 9.2.3.1 Tuning Parameters
          1. 9.2.3.1.1 Resistance Parameters
          2. 9.2.3.1.2 KMC and KMC_SCALE
            1. 9.2.3.1.2.1 Case I
            2. 9.2.3.1.2.2 Case II
              1. 9.2.3.1.2.2.1 Method 1: Tuning from Scratch
                1. 9.2.3.1.2.2.1.1 Tuning KMC_SCALE
                2. 9.2.3.1.2.2.1.2 Tuning KMC
              2. 9.2.3.1.2.2.2 Method 2: Using the Proportionality factor
                1. 9.2.3.1.2.2.2.1 Working Example
      4. 9.2.4 Motor Voltage
      5. 9.2.5 Motor Current
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 DRV8215_STATUS Registers

Table 8-3 lists the memory-mapped registers for the DRV8215_STATUS registers. All register offset addresses not listed in Table 8-3 should be considered as reserved locations and the register contents should not be modified.

Table 8-3 DRV8215_STATUS Registers
OffsetAcronymRegister NameSection
0hFAULT_STATUSVarious fault registers' status.Section 8.1.1
1hRC_STATUS1Status Registers - 1.Section 8.1.2
2hRC_STATUS2Status Registers - 2.Section 8.1.3
3hRC_STATUS3Status Registers - 3.Section 8.1.4
4hREG_STATUS1Regulation Status Registers - (1/5).Section 8.1.5
5hREG_STATUS2Regulation Status Registers - (2/5).Section 8.1.6
6hREG_STATUS3Regulation Status Registers - (3/5).Section 8.1.7
7hREG_STATUS4Regulation Status Registers - (4/5).Section 8.1.8
8hREG_STATUS5Regulation Status Registers - (5/5).Section 8.1.9

Complex bit access types are encoded to fit into small table cells. Table 8-4 shows the codes that are used for access types in this section.

Table 8-4 DRV8215_STATUS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

8.1.1 FAULT_STATUS Register (Offset = 0h) [Reset = 00h]

FAULT_STATUS is shown in Table 8-5.

Return to the Summary Table.

Status of various fault and protection bits.

Table 8-5 FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation.
6RESERVEDR0h
5STALLR0h When this bit is 1b, it indicates motor stall.
4OCPR0h 0b during normal operation, 1b if OCP event occurs.
3OVPR0h 0b during normal operation, 1b if OVP event occurs.
2TSDR0h 0b during normal operation, 1b if TSD event occurs.
1NPORR0h Reset and latched low if VCC>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command.
After power up, automatically latched high once CLR_FLT command is issued.
Refer to Section 7.3.7.3 for further explanation.
0RSVDR0h Reserved.

8.1.2 RC_STATUS1 Register (Offset = 1h) [Reset = 00h]

RC_STATUS1 is shown in Table 8-6.

Return to the Summary Table.

Estimated speed of motor ripples.

Table 8-6 RC_STATUS1 Register Field Descriptions
BitFieldTypeResetDescription
7-0SPEEDR0h Outputs the motor current ripple speed estimated by an internal algorithm.

8.1.3 RC_STATUS2 Register (Offset = 2h) [Reset = 00h]

RC_STATUS2 is shown in Table 8-7.

Return to the Summary Table.

Reserved.

Table 8-7 RC_STATUS2 Register Field Descriptions
BitFieldTypeResetDescription
7-0RSVDR0h Reserved.

8.1.4 RC_STATUS3 Register (Offset = 3h) [Reset = 00h]

RC_STATUS3 is shown in Table 8-8.

Return to the Summary Table.

Reserved.

Table 8-8 RC_STATUS3 Register Field Descriptions
BitFieldTypeResetDescription
7-0RSVDR0h Reserved.

8.1.5 REG_STATUS1 Register (Offset = 4h) [Reset = 00h]

REG_STATUS1 is shown in Table 8-9.

Return to the Summary Table.

Value corresponding to the output voltage across the motor terminals.

Table 8-9 REG_STATUS1 Register Field Descriptions
BitFieldTypeResetDescription
7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and B0h corresponds to 11 V.

8.1.6 REG_STATUS2 Register (Offset = 5h) [Reset = 00h]

REG_STATUS2 is shown in Table 8-10.

Return to the Summary Table.

Output corresponding to current flowing through the motor.

Table 8-10 REG_STATUS2 Register Field Descriptions
BitFieldTypeResetDescription
7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits.

8.1.7 REG_STATUS3 Register (Offset = 6h) [Reset = 00h]

REG_STATUS3 is shown in Table 8-11.

Return to the Summary Table.

Internal pwm duty cycle.

Table 8-11 REG_STATUS3 Register Field Descriptions
BitFieldTypeResetDescription
7-6RSVDR0h Reserved.
5-0DUTY_READR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated.
The range of duty cycle is 0% (000000b) to 100% (111111b).
Refer to Section 7.3.6 for further explanation on the internal PWM generation scheme.

8.1.8 REG_STATUS4 Register (Offset = 7h) [Reset = 00h]

REG_STATUS4 is shown in Table 8-12.

Return to the Summary Table.

Reserved.

Table 8-12 REG_STATUS4 Register Field Descriptions
BitFieldTypeResetDescription
7-0RSVDR0h Reserved.

8.1.9 REG_STATUS5 Register (Offset = 8h) [Reset = 00h]

REG_STATUS5 is shown in Table 8-13.

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Reserved.

Table 8-13 REG_STATUS5 Register Field Descriptions
BitFieldTypeResetDescription
7-0RSVDR0h Reserved.