SLVSHO3 April   2024 DRV8235

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Operating Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Summary of Features
      3. 7.3.3 Bridge Control
      4. 7.3.4 Current Sense and Regulation (IPROPI)
        1. 7.3.4.1 Current Sensing
        2. 7.3.4.2 Current Regulation
          1. 7.3.4.2.1 Fixed Off-Time Current Regulation
          2. 7.3.4.2.2 Cycle-By-Cycle Current Regulation
      5. 7.3.5 Stall Detection
      6. 7.3.6 Motor Voltage and Speed Regulation
        1. 7.3.6.1 Internal Bridge Control
        2. 7.3.6.2 Setting Speed/Voltage Regulation Parameters
          1. 7.3.6.2.1 Speed and Voltage Set
          2. 7.3.6.2.2 Speed Scaling Factor
            1. 7.3.6.2.2.1 Target Speed Setting Example
          3. 7.3.6.2.3 Motor Resistance Inverse
          4. 7.3.6.2.4 Motor Resistance Inverse Scale
          5. 7.3.6.2.5 KMC Scaling Factor
          6. 7.3.6.2.6 KMC
          7. 7.3.6.2.7 VSNS_SEL
        3. 7.3.6.3 Soft-Start and Soft-Stop
          1. 7.3.6.3.1 TINRUSH
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 Overcurrent Protection (OCP)
        2. 7.3.7.2 Thermal Shutdown (TSD)
        3. 7.3.7.3 VM Undervoltage Lockout (VM UVLO)
        4. 7.3.7.4 Overvoltage Protection (OVP)
        5. 7.3.7.5 nFAULT Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Communication
        1. 7.5.1.1 I2C Write
        2. 7.5.1.2 I2C Read
  9. 8 Register Map
    1. 8.1 DRV8235_STATUS Registers
    2. 8.2 DRV8235_CONFIG Registers
    3. 8.3 DRV8235_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Brushed DC Motor
      1. 9.2.1 Design Requirements
      2. 9.2.2 Stall Detection
        1. 9.2.2.1 Application Description
          1. 9.2.2.1.1 Stall Detection Timing
          2. 9.2.2.1.2 Hardware Stall Threshold Selection
      3. 9.2.3 Motor Speed and Voltage Regulation Application
        1. 9.2.3.1 Tuning Parameters
          1. 9.2.3.1.1 Resistance Parameters
          2. 9.2.3.1.2 KMC and KMC_SCALE
            1. 9.2.3.1.2.1 Case I
            2. 9.2.3.1.2.2 Case II
              1. 9.2.3.1.2.2.1 Method 1: Tuning from Scratch
                1. 9.2.3.1.2.2.1.1 Tuning KMC_SCALE
                2. 9.2.3.1.2.2.1.2 Tuning KMC
              2. 9.2.3.1.2.2.2 Method 2: Using the Proportionality factor
                1. 9.2.3.1.2.2.2.1 Working Example
      4. 9.2.4 Motor Voltage
      5. 9.2.5 Motor Current
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2 DRV8235_CONFIG Registers

Table 8-14 lists the memory-mapped registers for the DRV8235_CONFIG registers. All register offset addresses not listed in Table 8-14 should be considered as reserved locations and the register contents should not be modified.

Table 8-14 DRV8235_CONFIG Registers
OffsetAcronymRegister NameSection
9hCONFIG0Configuration Registers - Faults (1/5).Section 8.2.1
AhCONFIG1Configuration Registers - (2/5).Section 8.2.2
BhCONFIG2Configuration Registers - (3/5).Section 8.2.3
ChCONFIG3Configuration Registers - (4/5).Section 8.2.4
DhCONFIG4Configuration Registers - (5/5).Section 8.2.5

Complex bit access types are encoded to fit into small table cells. Table 8-15 shows the codes that are used for access types in this section.

Table 8-15 DRV8235_CONFIG Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.2.1 CONFIG0 Register (Offset = 9h) [Reset = 60h]

CONFIG0 is shown in Table 8-16.

Return to the Summary Table.

Enable/Disable various faults like OCP, OVP, STALL, etc.

Table 8-16 CONFIG0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_OUTR/W0h 0b: All driver FETs are Hi-Z.
1b: Enables the driver outputs.
6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature.
Refer to Section 7.3.7.4 for further explanation.
5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b.
Refer to EN_STALL configuration under Section 7.3.5 for further explanation.
4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value.
1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage.
3-2RSVDR0h Reserved
1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset.
0DUTY_CTRLR/W0h 0b: User cannot program duty cycle manually.
1b: When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to PROG_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b).

8.2.2 CONFIG1 Register (Offset = Ah) [Reset = 00h]

CONFIG1 is shown in Table 8-17.

Return to the Summary Table.

Configure the inrush time (1/2).

Table 8-17 CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
7-0TINRUSH_LSBR/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current.
Refer to Section 7.3.6.3.1 for further explanation.

8.2.3 CONFIG2 Register (Offset = Bh) [Reset = 00h]

CONFIG2 is shown in Table 8-18.

Return to the Summary Table.

Configure the inrush time (2/2).

Table 8-18 CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0TINRUSH_MSBR/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current.
Refer to Section 7.3.6.3.1 for further explanation.

8.2.4 CONFIG3 Register (Offset = Ch) [Reset = 63h]

CONFIG3 is shown in Table 8-19.

Return to the Summary Table.

Enable/Disable various device modes like IMODE, SMODE, and blanking time.

Table 8-19 CONFIG3 Register Field Descriptions
BitFieldTypeResetDescription
7-6IMODER/W1h Determines the behavior of current regulation.
Refer to IMODE configuration under Section 7.3.4.2 for further explanation.
5SMODER/W1h Programs device response to a stall condition.
Refer to SMODE configuration under Section 7.3.5 for further explanation.
4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b.
Refer to Section 7.3.5 for further explanation.
3TBLANKR/W0h Sets the current sense blanking time.
If set to 0b, tBLANK=1.8µs.
If set to 1b, tBLANK=1.0µs.
2TDEGR/W0h Sets the current regulation and stall detection deglitch time.
If set to 0b, tDEG=2µs.
If set to 1b, tDEG=1µs.
1OCP_MODER/W1h Programs device response to an overcurrent event.
If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT.
If set to 1b, device performs auto-retry after time tretry in case of an OCP event.
Refer to Section 7.3.7.1 for further explanation.
0TSD_MODER/W1h Programs device response to an overtemperature event.
If set to 0b, device is latched off in case of a TSD event.
If set to 1b, device performs auto-retry when TJ<TTSD–THYS.

8.2.5 CONFIG4 Register (Offset = Dh) [Reset = 38h]

CONFIG4 is shown in Table 8-20.

Return to the Summary Table.

Configure the report registers like RC_REP and STALL_REP.

Table 8-20 CONFIG4 Register Field Descriptions
BitFieldTypeResetDescription
7-6RSVDR0h Reserved.
5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin.
When set to 1b, nFAULT is low whenever stall is detected.
When set to 0b, stall is not reported on nFAULT output.
Refer to Section 7.3.5 for further explanation.
4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode.
1b: nFAULT is pulled low when H-Bridge enters internal current regulation.
0b: nFAULT is not pulled low when H-Bridge enters internal current regulation.
Refer to Section 7.3.4.2.2 for further explanation.
3PMODER/W1h Switch between phase/enable mode and PWM mode.
0b: PH/EN.
1b: PWM.
2I2C_BCR/W0h Decides the H-Bridge Control Interface.
0b: Bridge control configured by INx pins.
1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2.
1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b.
0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b.