SLVSHO3 April   2024 DRV8235

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Operating Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Summary of Features
      3. 7.3.3 Bridge Control
      4. 7.3.4 Current Sense and Regulation (IPROPI)
        1. 7.3.4.1 Current Sensing
        2. 7.3.4.2 Current Regulation
          1. 7.3.4.2.1 Fixed Off-Time Current Regulation
          2. 7.3.4.2.2 Cycle-By-Cycle Current Regulation
      5. 7.3.5 Stall Detection
      6. 7.3.6 Motor Voltage and Speed Regulation
        1. 7.3.6.1 Internal Bridge Control
        2. 7.3.6.2 Setting Speed/Voltage Regulation Parameters
          1. 7.3.6.2.1 Speed and Voltage Set
          2. 7.3.6.2.2 Speed Scaling Factor
            1. 7.3.6.2.2.1 Target Speed Setting Example
          3. 7.3.6.2.3 Motor Resistance Inverse
          4. 7.3.6.2.4 Motor Resistance Inverse Scale
          5. 7.3.6.2.5 KMC Scaling Factor
          6. 7.3.6.2.6 KMC
          7. 7.3.6.2.7 VSNS_SEL
        3. 7.3.6.3 Soft-Start and Soft-Stop
          1. 7.3.6.3.1 TINRUSH
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 Overcurrent Protection (OCP)
        2. 7.3.7.2 Thermal Shutdown (TSD)
        3. 7.3.7.3 VM Undervoltage Lockout (VM UVLO)
        4. 7.3.7.4 Overvoltage Protection (OVP)
        5. 7.3.7.5 nFAULT Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Communication
        1. 7.5.1.1 I2C Write
        2. 7.5.1.2 I2C Read
  9. 8 Register Map
    1. 8.1 DRV8235_STATUS Registers
    2. 8.2 DRV8235_CONFIG Registers
    3. 8.3 DRV8235_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Brushed DC Motor
      1. 9.2.1 Design Requirements
      2. 9.2.2 Stall Detection
        1. 9.2.2.1 Application Description
          1. 9.2.2.1.1 Stall Detection Timing
          2. 9.2.2.1.2 Hardware Stall Threshold Selection
      3. 9.2.3 Motor Speed and Voltage Regulation Application
        1. 9.2.3.1 Tuning Parameters
          1. 9.2.3.1.1 Resistance Parameters
          2. 9.2.3.1.2 KMC and KMC_SCALE
            1. 9.2.3.1.2.1 Case I
            2. 9.2.3.1.2.2 Case II
              1. 9.2.3.1.2.2.1 Method 1: Tuning from Scratch
                1. 9.2.3.1.2.2.1.1 Tuning KMC_SCALE
                2. 9.2.3.1.2.2.1.2 Tuning KMC
              2. 9.2.3.1.2.2.2 Method 2: Using the Proportionality factor
                1. 9.2.3.1.2.2.2.1 Working Example
      4. 9.2.4 Motor Voltage
      5. 9.2.5 Motor Current
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6.1 Internal Bridge Control

For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient.

The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET.

When speed/voltage regulation mode is active, an internal bridge control scheme is employed. DUTY_CTRL must be set to 0b. The duty cycle cannot be manually programmed by the user.

  • If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased.

  • If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased.

  • During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity.

  • During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge.

  • If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver.

Note:

  1. During Speed/Voltage regulation, the duty cycle can be read from the DUTY_READ register
  2. PWM_FREQ sets the PWM frequency for internal PWM generation. Variation around the value of PWM_FREQ is ±30%.

Table 7-11 PWM_FREQ Settings
Bit Value
0b 50 kHz
1b 25 kHz
Note:

In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b.

Note:

When Speed/Voltage regulation is inactive, the user can still PWM internally. To do this, set DUTY_CTRL to 1b and program the duty cycle value into PROG_DUTY. Please note that in this case, I2C_BC is used to decide if the information about the direction or rotation (Forward/Reverse/Coast/Brake/Sleep) is extracted:

  1. Externally, from the EN/IN1 and PH/IN2 pins; I2C_BC=0b), or
  2. Internally (from the I2C_EN_IN1 and I2C_PH_IN2 bits; I2C_BC=1b)
Please note that the setting for PMODE does not matter in this case.

As an example, if the settings in Table 7-12 are followed, the device PWMs at 50kHz with approximately 50% duty cycle in the forward direction.

Table 7-12 Example settings
Bit Value
I2C_BC 1b
DUTY_CTRL 1b
PMODE 1b
PWM_FREQ 0b
PROG_DUTY 011111b
I2C_EN_IN1 1b
I2C_PH_IN2 0b