SLVSGY7A November   2023  – March 2024 DRV8242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN (20) package
    2. 5.2 SPI Variant
      1. 5.2.1 VQFN (20) package
      2. 5.2.2 VQFN (20) package
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information VQFN-RHL package
    5. 6.5  Electrical Characteristics
    6. 6.6  Transient Thermal Impedance & Current Capability
    7. 6.7  SPI Timing Requirements
    8. 6.8  Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
    9. 6.9  Wake-up Transients
      1. 6.9.1 HW Variant
      2. 6.9.2 SPI Variant
    10. 6.10 Fault Reaction Transients
      1. 6.10.1 Retry setting
      2. 6.10.2 Latch setting
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Power On Reset (POR)
        8. 7.3.4.8 Event Priority
    4. 7.4 Device Functional States
      1. 7.4.1 SLEEP State
      2. 7.4.2 STANDBY State
      3. 7.4.3 Wake-up to STANDBY State
      4. 7.4.4 ACTIVE State
      5. 7.4.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
    5. 7.5 Programming - SPI Variant Only
      1. 7.5.1 SPI Interface
      2. 7.5.2 Standard Frame
      3. 7.5.3 SPI Interface for Multiple Peripherals
        1. 7.5.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only

  • Device state: ACTIVE - high-side recirculation
  • Mechanism and threshold: On-state diagnostics (OLA) can detect an open load detection in the ACTIVE state during high-side recirculation. This includes high-side load connected directly to VM or through a high-side FET on the other half-bridge. During a PWM switching transition, the inductive load current re-circulates into VM through the HS body diode when the LS FET is turned OFF. The device looks for a voltage spike on OUTx above VM during the brief dead time, before the HS FET is turned ON. To observe the voltage spike, this load current needs to be higher than the pull down current (IPD_OLA) on the output asserted by the FET driver. Device has configurable bit OLA_FLTR (CONFIG2) for either "16" or "1024" consecutive re-circulation switching cycles with absence of this voltage spike to indicate a loss of load inductance or increase in load resistance and is detected as an OLA fault.
  • Action:
    • nFAULT pin is asserted low
    • Output - normal function maintained
    • IPROPI pin - normal function maintained
  • Reaction configurable between latch setting and retry setting. In retry setting, OLA fault is automatically cleared with the detection of either "16" or "1024" consecutive voltage spikes during re-circulation switching cycles.
  • OLA Fault Behavior during direction change:
    • Retry mode - If an open load condition is detected on OUTx, OLAx bit is set if condition persists for longer than the filter time. OLAx filter is cleared on direction change.
    • Latch mode - If an open load condition is detected on OUTx, OLAx is set if condition persists for longer than the filter time. OLAx remains latched until a CLR_FLT command is issued. OLAx filter is cleared on direction change.
  • OLA Fault Behavior during CLR_FLT command:
    • Retry mode - CLR_FLT command is not used.
    • Latch mode - If an open load condition is detected on OUT1, OLA1 is set if condition persists for longer than the filter time. OLAx remains latched until a CLR_FLT command is issued, which is cleared regardless of open load condition. If the condition does exist, OLA fault will be reported again after the filter time.
This monitoring is optional and can be disabled.

GUID-20200821-CA0I-XJWB-DNM7-XWN9ZCQ5RBDC-low.svg Figure 7-7 On-State Diagnostics