SLVSGY7A November   2023  – March 2024 DRV8242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN (20) package
    2. 5.2 SPI Variant
      1. 5.2.1 VQFN (20) package
      2. 5.2.2 VQFN (20) package
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information VQFN-RHL package
    5. 6.5  Electrical Characteristics
    6. 6.6  Transient Thermal Impedance & Current Capability
    7. 6.7  SPI Timing Requirements
    8. 6.8  Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
    9. 6.9  Wake-up Transients
      1. 6.9.1 HW Variant
      2. 6.9.2 SPI Variant
    10. 6.10 Fault Reaction Transients
      1. 6.10.1 Retry setting
      2. 6.10.2 Latch setting
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Power On Reset (POR)
        8. 7.3.4.8 Event Priority
    4. 7.4 Device Functional States
      1. 7.4.1 SLEEP State
      2. 7.4.2 STANDBY State
      3. 7.4.3 Wake-up to STANDBY State
      4. 7.4.4 ACTIVE State
      5. 7.4.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
    5. 7.5 Programming - SPI Variant Only
      1. 7.5.1 SPI Interface
      2. 7.5.2 Standard Frame
      3. 7.5.3 SPI Interface for Multiple Peripherals
        1. 7.5.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

4.5 V ≤ VVM ≤ 35 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM)
VVM_REV Supply pin voltage during reverse current Unpowered state, IVM = - 5 A 1.85 V
IVMQ VM current in SLEEP state VVM = 13.5 V, TA = 25°C, nSLEEP = 0 1.5 µA
VVM = 13.5 V, TA = 125°C, nSLEEP = 0 5.8 µA
IVMS VM current in STANDBY state with drivers HiZ VVM = 13.5 V, nSLEEP = 1'b1, DRVOFF = 1'b1, EN/IN1 = PH/IN2 = 1'b0 3 5 mA
tRESET Filter time on nSLEEP pin to register nSLEEP_RESET pulse nSLEEP = 1'b1 to 1'b0 , HW variant only 5 20 µs
tSLEEP Filter time on nSLEEP pin to register SLEEP command , HW variant only nSLEEP = 1'b1 to 1'b0 40 120 µs
tSLEEP_SPI Filter time on nSLEEP pin to register SLEEP command , SPI variant only nSLEEP = 1'b1 to 1'b0 5 20 µs
tCOM Time from WAKEUP till nFAULT pin gets asserted low, after which device communication is available nSLEEP = 1'b0 to 1'b1 0.4 ms
tREADY Time from WAKEUP till device ready to process driver inputs nSLEEP = 1'b0 to 1'b1 1 ms
CONTROLLER (nSLEEP, DRVOFF, EN/IN1, PH/IN2,) and SPI INPUTS (SDI, SDO, nSCS, SCLK)
VIL Input logic low voltage on nSLEEP pin 0.65 V
VIH Input logic high voltage on nSLEEP pin 1.55 V
VIHYS Input hysteresis on nSLEEP pin 0.2 V
VIL Input logic low voltage DRVOFF, inputs pins, SPI pins 0.7 V
VIH Input logic high voltage DRVOFF, inputs pins, SPI pins 1.5 V
VIHYS Input hysteresis DRVOFF, inputs pins, SPI pins 0.1 V
RPD_nSLEEP Input pull-down resistance on nSLEEP to GND Measured at min VIH level 100 400 kΩ
RPU_DRVOFF Input pull-up resistance on DRVOFF to 5V internal Measured at min VIH level 180 550 kΩ
RPD_EN/IN1 Input pull-down resistance on EN/IN1 to GND Measured at max VIL level 200 500 kΩ
RPD_PH/IN2 Input pull-down resistance on PH/IN2 to GND Measured at max VIL level 200 500 kΩ
RPU_nSCS Input pull-up resistance on nSCS to 5V internal (diode blocked), SPI variant only Measured at min VIH level 200 500 kΩ
RPD_SDI Input pull-down resistance on SDI to GND, SPI variant only Measured at max VIL level 150 500 kΩ
RPD_SCLK Input pull-down resistance on SCLK to GND, SPI variant only Measured at min VIH level 150 500 kΩ
VOL_SDO Output logic low voltage, SPI variant only 0.5 mA sink into the pin 0.4 V
VOH_SDO5 Output logic high voltage, SPI variant only - 5V interface 0.5 mA source from the pin, V(nSLEEP) = 5 V, VM > 7 V, S variant 4.1 V
VOH_SDO Output logic high voltage, SPI variant only - 3.3V interface 0.5 mA source from the pin, V(nSLEEP) = 3.3 V, VM > 5 V, S variant 2.7 V
VOH_SDO5 Output logic high voltage, SPI variant only - 5V interface 0.5 mA source from the pin, V(nSLEEP) = 5 V, VDD = 5V, P variant 4.5 V
VOH_SDO5_NL Output logic high voltage, SPI variant only - 5V interface No current from pin, V(nSLEEP) = 5 V, VM > 7 V, S variant 5.5 V
VOH_SDO_NL Output logic high voltage, SPI variant only - 3.3V interface No current from pin, V(nSLEEP) = 3.3 V, VM > 5 V, S variant 3.8 V
6 LEVEL HARDWIRED CONFIGURATION for ITRIP, SR and DIAG pins
RLVL1 Short to GND Phyically shorted to GND 10 Ω
RLVL2 Resistor to GND +/- 10% resistors 7.4 8.2 9 kΩ
RLVL3 Resistor to GND +/- 10% resistors 19.8 22 24.2 kΩ
RLVL4 Resistor to GND +/- 10% resistors 42.3 47 51.7 kΩ
RLVL5 Resistor to GND +/- 10% resistors 90 100 110 kΩ
RLVL6 No connect Floating (no connect) 250 kΩ
2 LEVEL HARDWIRED CONFIGURATION for MODE pin
RLVL1 Resistor to GND Phyically shorted to GND 10 Ω
RLVL2 No connect Floating (no connect) 250 kΩ
DRIVER OUTPUT (OUTx)
RHS_DS(on) High-side MOSFET on resistance, RHL VVM = 13.5 V, IO = 2 A, TJ = 25°C 125 mΩ
VVM = 13.5 V, IO = 2 A, TJ = 150°C 220 mΩ
RLS_DS(on) Low-side MOSFET on resistance, RHL VVM = 13.5 V, IO = 2 A, TJ = 25°C 125 mΩ
VVM = 13.5 V, IO = 2 A, TJ = 150°C 220 mΩ
VSD_LS Body diode forward voltage IOUTx = -2 A (Out of the pin) -1.5 -0.9 -0.4 V
VSD_HS Body diode forward voltage IOUTx = 2 A (Into pin) 0.4 0.9 1.5 V
RHIZ OUTx resistance to GND in HiZ, V(OUTx) = VM = 13.5 V SR = 3'b000 or 3'b001 or 3'b010 or 3'b111 or LVL2 or LVL5 7 82 kΩ
SR = 3'b011 or LVL3 15 27 kΩ
SR = 3'b100 or LVL4 13 21 kΩ
SR = 3'b101 or LVL1 10 18 kΩ
SR = 3'b110 or LVL6 7 12 kΩ
SRLSOFF Output voltage rise time, 10% - 90%, HS RECIRC SR = 3'b000 or LVL2 1.1 V/µs
SR = 3'b001 (SPI only) 5 V/µs
SR = 3'b010 (SPI only) 10 V/µs
SR = 3'b011 or LVL3 15 V/µs
SR = 3'b100 or LVL4 20 V/µs
SR = 3'b101 or LVL1 25 V/µs
SR = 3'b110 or LVL6 40 V/µs
SR = 3'b111 or LVL5 50 V/µs
tPD_LSOFF Propagation time during output voltage rise, HS RECIRC SR = 3'b000 or LVL2 0.3 µs
SR = 3'b001 (SPI only) 0.3 µs
SR = 3'b010 (SPI only) 0.3 µs
SR = 3'b011 or LVL3 0.3 µs
SR = 3'b100 & 3'b101 or LVL4 & LVL1 0.3 µs
SR = 3'b110 & 3'b111 or LVL6 & LVL5 (SPI only) 0.27 µs
tDEAD_LSOFF Dead time during output voltage rise, HS RECIRC All SRs 0.7 µs
SRLSON Output voltage fall time, 90% - 10%, HS RECIRC SR = 3'b000 or LVL2 1 V/µs
SR = 3'b001 (SPI only) 5 V/µs
SR = 3'b010 (SPI only) 10 V/µs
SR = 3'b011 or LVL3 17 V/µs
SR = 3'b100 or LVL4 22 V/µs
SR = 3'b101 or LVL1 28 V/µs
SR = 3'b110 or LVL6 46 V/µs
SR = 3'b111 or LVL5 58 V/µs
tPD_LSON Propagation time during output voltage fall, HS RECIRC SR = 3'b000 or LVL2 0.18 µs
SR = 3'b001 (SPI only) 0.18 µs
SR = 3'b010 (SPI only) 0.18 µs
SR = 3'b011 or LVL3 0.18 µs
SR = 3'b100 or LVL4 0.18 µs
SR = 3'b101 or LVL1 0.18 µs
SR = 3'b110 or 3'b111 or LVL6 or& LVL5 0.18 µs
tDEAD_LSON Dead time during output voltage fall, HS RECIRC SR = 3'b000 or LVL2 3 µs
SR = 3'b001 (SPI only) 0.9 µs
SR = 3'b010 (SPI only) 0.8 µs
SR = 3'b011 or LVL3 0.8 µs
All other SRs 0.8 µs
MatchSRLS Output voltage rise and fall slew rate matching, High side recirculation only All SRs -20 20 %
CURRENT SENSE AND REGULATION (IPROPI, VREF)
AIPROPI_TOP Current scaling factor, RHL Current range: 0.5 A to 2 A
 		 1354 1425 1496 A/A
AIPROPI_MID Current scaling factor, RHL Current range: 0.1 A to 0.5 A 1283 1425 1567 A/A
AIPROPI_BOT Current scaling factor, RHL Current range: 0.05 A to 0.1 A 1140 1425 1710 A/A
AIPROPI_M_TOP Current matching between the two half bridges in the TOP range –2 2 %
OffsetIPROPI Offset current on IPROPI at zero load current Measured in active state 15 µA
BWIPROPI_SNS Bandwidth of the internal IPROPI sense circuit No external cap on IPROPI .4 MHz
VIPROPI_LIM Internal clamping voltage on IPROPI 4 5.5 V
VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation ITRIP = 3'b001 or LVL2 1.06 1.18 1.3 V
ITRIP = 3'b010 (SPI only) 1.27 1.41 1.55 V
ITRIP = 3'b011 (SPI only) 1.49 1.65 1.82 V
ITRIP = 3'b100 or LVL3 1.78 1.98 2.18 V
ITRIP = 3'b101 or LVL4 2.08 2.31 2.54 V
ITRIP = 3'b110 or LVL5 2.38 2.64 2.9 V
ITRIP = 3'b111 or LVL6 2.67 2.97 3.27 V
tOFF ITRIP regulation - off time TOFF = 2'b00 (SPI only) 16 20 25 µs
TOFF = 2'b01 (SPI). Only choice for HW 24 30 36 µs
TOFF = 2'b10 (SPI only) 33 40 48 µs
TOFF = 2'b11 (SPI only) 41 50 61 µs
PROTECTION CIRCUITS
VVMOV VM over voltage threshold while rising VMOV_SEL = 2'b00 (SPI), Only choice in HW variant 33.6 37 V
VMOV_SEL = 2'b01 (SPI only) 28 31 V
VMOV_SEL = 2'b10 (SPI only) 18 21 V
VVMOV_HYS VM OV hysteresis VM OV Hysteresis 0.6 V
VVMUV VM Under Voltage VM falling 4.2 4.5 V
VVMUV_HYS VM UV hysteresis VM UV Hysteresis 0.2 V
tVMUV VM UV deglitch time 10 12 19 µs
tVMOV VM OV deglitch time 10 12 19 µs
VMPOR_FALL VM voltage at which device goes into POR Applicable for HW & SPI "S" variant 3.6 V
VMPOR_RISE VM voltage at which device comes out of POR Applicable for HW & SPI "S" variant 3.9 V
VDDPOR_FALL VDD voltage at which device goes into POR Applicable for SPI "P" variant 3.5 V
VDDPOR_RISE VDD voltage at which device comes out of POR Applicable for SPI "P" variant 3.8 V
IOCP_HS Over current protection threshold on the high side OCP_SEL = 2'b00 (SPI), Only choice for HW 6 12 A
OCP_SEL = 2'b10 (SPI only) 4.5 9 A
OCP_SEL = 2'b01 (SPI only) 3 6 A
IOCP_LS Over current protection threshold on the low side OCP_SEL = 2'b00 (SPI), Only choice for HW 6 12 A
OCP_SEL = 2'b10 (SPI only) 4.5 9 A
OCP_SEL = 2'b01 (SPI only) 3 6 A
tOCP Overcurrent protection deglitch time TOCP_SEL = 2'b00 (SPI), Only choice for HW 4.5 6 7.3 µs
TOCP_SEL = 2'b01 (SPI only) 2.2 3 4.1 µs
TOCP_SEL = 2'b10 (SPI only) 1.1 1.75 2.3 µs
TOCP_SEL = 2'b11 (SPI only) 0.15 0.35 0.55 µs
TTSD Thermal shutdown temperature 155 170 185 °C
tTSD Thermal shutdown deglitch time 10 12 19 µs
THYS Thermal shutdown hysteresis 30 °C
tRETRY Overcurrent protection retry time 4.1 5 6.2 ms
tCLEAR Fault free operation time to auto-clear nFAULT in RETRY fault reaction mode 80 200 µs
tCLEAR_TSD Fault free operation time to auto-clear nFAULT in RETRY fault reaction mode 4.2 6.7 ms
InFAULT_PD Pull down current on nFAULT pin to indicate fault VnFAULT = 0.3 V 5 mA
OPEN LOAD DETECTION CIRCUITS
RS_GND Resistance on OUT to GND that will be detected as short 1 KΩ
RS_VM Resistance on OUT to VM that will be detected as short 1 KΩ
ROPEN_FB Resistance between OUTx that will be detected as open, PH/EN or PWM mode 1.5 KΩ
VOLP_REFH OLP Comparator Reference High 2.65 V
VOLP_REFL OLP Comparator Reference Low 2 V
ROLP_PU OUTx resistance to internal 5V during OLP VOUTx = VOLP_REFH + 0.1V 1 kΩ
ROLP_PD OUTx resistance to GND during OLP VOUTx = VOLP_REFL - 0.1V 1 kΩ
IPD_OLA Internal sink current on OUT to GND during dead-time in high-side recirculation SR = 3'b000 or 3'b001 or 3'b010 or 3'b111 or LVL2 or LVL5 0.1 3.5 mA
SR = 3'b011 or LVL3 0.5 0.8 mA
SR = 3'b100 or LVL4 0.6 1 mA
SR = 3'b101 or LVL1 0.5 1.5 mA
SR = 3'b110 or LVL6 1 2 mA
VOLA_REF OLA Comparator Reference with respect to VM 0.25 V