SLOSE50 Data sheet

SLOSE50A April 2020 – June 2021

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGE|24
- MPQF124G
PWP|28
- MPDS373B

Thermal pad, mechanical data (Package|Pins)

RGE|24
- QFND008AA

Orderable Information

6.5 Electrical Characteristics

Typical values are at T_A = 25°C and V_VM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (VM, DVDD)
I_VM	VM operating supply current	nSLEEP = 1, No motor load		4	5.5	mA
I_VMQ	VM sleep mode supply current	nSLEEP = 0		2	4	μA
t_SLEEP	Sleep time	nSLEEP = 0 to sleep-mode	120			μs
t_RESET	nSLEEP reset pulse	nSLEEP low to clear fault	20		40	μs
t_WAKE	Wake-up time	nSLEEP = 1 to output transition		0.8	1.2	ms
t_ON	Turn-on time	VM > UVLO to output transition		0.8	1.2	ms
V_DVDD	Internal regulator voltage	No external load, 6 V < V_VM < 48 V	4.75	5	5.25	V
V_DVDD	Internal regulator voltage	No external load, V_VM = 4.5V	4.2	4.35		V
CHARGE PUMP (VCP, CPH, CPL)
V_VCP	VCP operating voltage	6 V < V_VM < 48 V		V_VM + 5		V
f_(VCP)	Charge pump switching frequency	V_VM > UVLO; nSLEEP = 1		360		kHz
LOGIC-LEVEL INPUTS (PH, EN, IN1, IN2, nSLEEP)
V_IL	Input logic-low voltage		0		0.6	V
V_IH	Input logic-high voltage		1.5		5.5	V
V_HYS	Input logic hysteresis			150		mV
I_IL	Input logic-low current	V_IN = 0 V	–1		1	μA
I_IH	Input logic-high current	V_IN = 5 V			100	μA
t_PD	Propagation delay	PH, EN, INx input to current change		800		ns
QUAD-LEVEL INPUTS (DECAY, TOFF)
V_I1	Input logic-low voltage	Tied to GND	0		0.6	V
V_I2		330kΩ ± 5% to GND	1	1.25	1.4	V
V_I3	Input Hi-Z voltage	Hi-Z (>500kΩ to GND)	1.8	2	2.2	V
V_I4	Input logic-high voltage	Tied to DVDD	2.7		5.5	V
I_O	Output pull-up current			10		μA
CONTROL OUTPUTS (nFAULT)
V_OL	Output logic-low voltage	I_O = 5 mA			0.5	V
I_OH	Output logic-high leakage		–1		1	μA
MOTOR DRIVER OUTPUTS (OUT1, OUT2)
R_DS(ONH)	High-side FET on resistance	T_J = 25 °C, I_O = -1 A		82	100	mΩ
		T_J = 125 °C, I_O = -1 A		125	150	mΩ
		T_J = 150 °C, I_O = -1 A		140	175	mΩ
R_DS(ONL)	Low-side FET on resistance	T_J = 25 °C, I_O = 1 A		82	100	mΩ
		T_J = 125 °C, I_O = 1 A		125	150	mΩ
		T_J = 150 °C, I_O = 1 A		140	175	mΩ
t_SR	Output slew rate	VM = 24V, I_O = 1 A, Between 10% and 90%		240		V/µs
CURRENT REGULATION (VREF)
I_VREF	VREF Leakage Current	VREF = 3.3 V			8.25	μA
t_OFF	PWM off-time	TOFF = 0		7		μs
		TOFF = 1		16
		TOFF = Hi-Z		24
		TOFF = 330 kΩ to GND		32
ΔI_TRIP	I_TRIP Current Accuracy	0.5 A < I_TRIP < 1 A	-12		12	%
		1 A < I_TRIP < 2 A	-6		6
		2 A < I_TRIP < 5 A	-4		4
PROTECTION CIRCUITS
V_UVLO	VM UVLO lockout	VM falling, UVLO falling	4.1	4.25	4.35	V
V_UVLO	VM UVLO lockout	VM rising, UVLO rising	4.2	4.35	4.45	V
V_UVLO,HYS	Undervoltage hysteresis	Rising to falling threshold		100		mV
V_CPUV	Charge pump undervoltage	VCP falling		V_VM + 2		V
I_OCP	Overcurrent protection	Current through any FET	8			A
t_OCP	Overcurrent deglitch time			2		μs
T_OTSD	Thermal shutdown	Die temperature T_J	150	165	180	°C
T_{HYS_OTSD}	Thermal shutdown hysteresis	Die temperature T_J		20		°C