SLOSE50A April   2020  – June 2021

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
      2. 7.3.2 Current Regulation
      3. 7.3.3 Decay Modes
        1. 7.3.3.1 Mixed Decay
        2. 7.3.3.2 Fast Decay
        3. 7.3.3.3 Smart tune Dynamic Decay
        4. 7.3.3.4 Smart tune Ripple Control
        5. 7.3.3.5 Blanking time
      4. 7.3.4 Charge Pump
      5. 7.3.5 Linear Voltage Regulators
      6. 7.3.6 Logic and Quad-Level Pin Diagrams
        1. 7.3.6.1 nFAULT Pin
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.7.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.7.3 Overcurrent Protection (OCP)
        4. 7.3.7.4 Thermal Shutdown (OTSD)
        5.       Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4.      Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
          1. 8.2.2.1.1 Power Dissipation and Thermal Calculation
          2. 8.2.2.1.2 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

PIN TYPE DESCRIPTION
NAME PWP RGE
DRV8256E DRV8256P DRV8256E DRV8256P
DECAY 21 21 16 16 I Decay mode setting pin. Quad-level pin.
EN 25 — 20 — I Enable input. Logic high enables bridge; logic low disables the bridge Hi-Z.
IN1 — 25 — 20 I PWM input. Logic controls the state of H-bridge; internal pulldown.
IN2 — 24 — 19 I PWM input. Logic controls the state of H-bridge; internal pulldown.
OUT1 4, 5, 10, 11 4, 5, 10, 11 3, 6 3, 6 O Winding output. Connect to motor winding.
OUT2 6, 7, 8, 9 6, 7, 8, 9 4, 5 4, 5 O Winding output. Connect to motor winding.
PH 24 — 19 — I Phase input. Logic high drives current from OUT1 to OUT2.
VREF 17, 18 17, 18 12, 13 12, 13 I Reference voltage input pins. Voltage on these pins sets the full scale chopping current in H-bridge. The two pins must be tied together.
NC 20, 22, 23 20, 22, 23 15, 17, 18 15, 17, 18 I No Connect.
CPH 28 28 23 23 PWR Charge pump switching node. Connect a X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL.
CPL 27 27 22 22
GND 14 14 9 9 PWR Device ground. Connect to system ground.
TOFF 19 19 14 14 I Sets the decay mode off-time during current chopping; quad-level pin. Also sets the ripple current in smart tune ripple control mode.
DVDD 15 15 10 10 PWR Logic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
VCP 1 1 24 24 O Charge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM.
VM 2, 13 2, 13 1, 8 1, 8 PWR Power supply. Connect to motor supply voltage and bypass to PGND with two 0.01-μF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM.
PGND 3, 12 3, 12 2, 7 2, 7 PWR Power ground. Connect to system ground.
nFAULT 16 16 11 11 O Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
nSLEEP 26 26 21 21 I Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor.
PAD - - - - - Thermal pad. Connect to system ground.