SLVSCX2B
August 2015 – February 2016
DRV8305
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
SPI Timing Requirements (Slave Mode Only)
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Integrated Three-Phase Gate Driver
7.3.2
INHx/INLx: Gate Driver Input Modes
7.3.3
VCPH Charge Pump: High-Side Gate Supply
7.3.4
VCP_LSD LDO: Low-Side Gate Supply
7.3.5
GHx/GLx: Half-Bridge Gate Drivers
7.3.5.1
IDRIVE: Gate Driver Output Current
7.3.5.2
TDRIVE: Gate Driver State Machine
7.3.5.3
CSAs: Current Shunt Amplifiers
7.3.6
DVDD and AVDD: Internal Voltage Regulators
7.3.7
VREG: Voltage Regulator Output
7.3.8
Protection Features
7.3.8.1
Fault and Warning Classification
7.3.8.2
MOSFET Shoot-Through Protection (TDRIVE)
7.3.8.3
MOSFET Overcurrent Protection (VDS_OCP)
7.3.8.3.1
MOSFET dV/dt Turn On Protection (TDRIVE)
7.3.8.3.2
MOSFET Gate Drive Protection (GDF)
7.3.8.4
Low-Side Source Monitors (SNS_OCP)
7.3.8.5
Fault and Warning Operating Modes
7.3.9
Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
7.3.9.1
Overtemperature Warning (OTW) and Shutdown (OTSD) Protection
7.3.9.2
Reverse Supply Protection
7.3.9.3
MCU Watchdog
7.3.9.4
VREG Undervoltage (VREG_UV)
7.4
Device Functional Modes
7.4.1
Power Up Sequence
7.4.2
Standby State
7.4.3
Operating State
7.4.4
Sleep State
7.4.5
Limp Home or Fail Code Operation
7.5
Programming
7.5.1
SPI Communication
7.5.1.1
SPI
7.5.1.2
SPI Format
7.6
Register Maps
7.6.1
Status Registers
7.6.1.1
Warning and Watchdog Reset (Address = 0x1)
7.6.1.2
OV/VDS Faults (Address = 0x2)
7.6.1.3
IC Faults (Address = 0x3)
7.6.1.4
VGS Faults (Address = 0x4)
7.6.2
Control Registers
7.6.2.1
HS Gate Drive Control (Address = 0x5)
7.6.2.2
LS Gate Drive Control (Address = 0x6)
7.6.2.3
Gate Drive Control (Address = 0x7)
7.6.2.4
IC Operation (Address = 0x9)
7.6.2.5
Shunt Amplifier Control (Address = 0xA)
7.6.2.6
Voltage Regulator Control (Address = 0xB)
7.6.2.7
VDS Sense Control (Address = 0xC)
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Gate Drive Average Current
8.2.2.2
MOSFET Slew Rates
8.2.2.3
Overcurrent Protection
8.2.2.4
Current Sense Amplifiers
8.2.3
Application Curves
9
Power Supply Recommendations
9.1
Bulk Capacitance
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.2
Community Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PHP|48
MPQF051B
Thermal pad, mechanical data (Package|Pins)
PHP|48
PPTD118C
Orderable Information
SLVSCX2B_pm
slvscx2b_oa