SLVSCK2A April   2014  – February 2016 DRV8307

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hall Comparators
      2. 7.3.2  HALLOUT Output
      3. 7.3.3  Enable, Reset, and Clock Generation
      4. 7.3.4  Commutation
        1. 7.3.4.1 120° 3-Hall Commutation
        2. 7.3.4.2 120° Single-Hall Commutation
      5. 7.3.5  Braking
      6. 7.3.6  Output Pre-Drivers
      7. 7.3.7  Current Limit
      8. 7.3.8  Charge Pump
      9. 7.3.9  5-V Linear Regulator
      10. 7.3.10 Power Switch
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VM Overvoltage (VMOV)
        3. 7.3.11.3 Motor Overcurrent Protection (OCP)
        4. 7.3.11.4 Charge Pump Failure (CPFAIL)
        5. 7.3.11.5 Charge Pump Short (CPSC)
        6. 7.3.11.6 Rotor Lockup (RLOCK)
        7. 7.3.11.7 Overtemperature (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock PWM Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Hall Sensor Configurations and Connections
      2. 8.1.2 ENABLEn Considerations
      3. 8.1.3 Faster Starting and Stopping
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configurations and Functions

RHA Package
40-Pin (VQFN)
Top View
DRV8307 QFN_qfn_pin_diagram.eps

Pin Functions

PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NUMBER
POWER AND GROUND
CP1 30 I/O Charge pump flying capacitor Connect a 0.1-μF 35-V capacitor between CP1 and CP2
CP2 29 I/O
GND 26, PPAD I Ground reference. Terminal 26 and the Power Pad are internally connected. Connect to board GND
VCP 28 I/O Charge pump storage capacitor Connect a 1-μF 35-V ceramic capacitor to VM
VINT 25 I/O Internal 1.8-V core voltage regulator bypass Bypass to GND with a 1-μF 6.3-V ceramic capacitor
VM 27 I Motor supply voltage Connect to motor supply voltage.
Bypass to GND with a 0.1-μF ceramic capacitor, plus a large electrolytic capacitor (47 μF or larger is recommended), with a voltage rating of 1.5× to 2.5× VM.
VREG 24 O 5-V regulator output. Active when ENABLEn is active. Bypass to GND with a 0.1-μF 10-V ceramic capacitor. Can provide 5-V power to Hall sensors.
VSW 7 O Switched VM power output. When ENABLEn is active, VM is applied to this terminal. Can be used for powering Hall elements, along with added series resistance.
CONTROL
BRAKE 20 I Causes motor to brake. Polarity is programmable. Internal pulldown resistor.
PWM 19 I The clock input, used in clock frequency mode and clock PWM mode. Internal pulldown resistor.
DIR 21 I Sets motor rotation direction. Internal pulldown resistor.
ENABLEn 22 I Enables and disables the motor – active low. Internal pulldown resistor.
FAULTn 17 OD Fault indicator – active low when overcurrent, overtemperature, or rotor stall detected. Open-drain output.
HALLOUT 16 OD Outputs a TACH signal generated from the Hall U sensor. Open-drain output.
LOCKn 18 OD This open-drain output drives low when a spinning motor reaches a consistent speed, based on the period of Hall U.
RSVD 11 Reserved Can be floating or connected to ground.
RSVD 12
RSVD 13
RSVD 14
RSVD 15
RSVD 23
POWER STAGE INTERFACE
ISEN 31 I Low-side current sense resistor Connect to low-side current sense resistor
U 33 I Measures motor phase voltages for VFETOCP Connect to motor windings
V 36 I
W 39 I
UHSG 32 O High-side FET gate outputs Connect to high-side ½ H-bridge N-channel FET gate
VHSG 35 O
WHSG 38 O
ULSG 34 O Low-side FET gate outputs Connect to low-side ½ H-bridge N-channel FET gate
VLSG 37 O
WLSG 40 O
RSVD 8 Reserved Do not connect. Leave floating.
RSVD 9
RSVD 10
HU+ 1 I Hall sensor U positive input Connect to Hall sensors. Noise filter capacitors may be desirable, connected between the + and – Hall inputs.
HU– 2 I Hall sensor U negative input
HV+ 3 I Hall sensor V positive input
HV– 4 I Hall sensor V negative input
HW+ 5 I Hall sensor W positive input
HW– 6 I Hall sensor W negative input
(1) I = input, O = output, OD = open-drain output, I/O = input/output