SLOSE47A November   2020  – May 2022 DRV8434

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
      1. 6.6.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Mixed Decay for Increasing and Decreasing Current
        4. 7.3.6.4 Smart tune Dynamic Decay
        5. 7.3.6.5 Smart tune Ripple Control
        6. 7.3.6.6 PWM OFF Time
        7. 7.3.6.7 Blanking time
      7. 7.3.7  Charge Pump
      8. 7.3.8  Linear Voltage Regulators
      9. 7.3.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
        1. 7.3.9.1 nFAULT Pin
      10. 7.3.10 Protection Circuits
        1. 7.3.10.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.10.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.10.3 Overcurrent Protection (OCP)
          1. 7.3.10.3.1 Latched Shutdown
          2. 7.3.10.3.2 Automatic Retry
        4. 7.3.10.4 Open-Load Detection (OL)
        5. 7.3.10.5 Thermal Shutdown (OTSD)
          1. 7.3.10.5.1 Latched Shutdown
          2. 7.3.10.5.2 Automatic Retry
        6.       Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2.      52
      3. 7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      4. 7.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)
      5. 7.4.4 nSLEEP Reset Pulse
      6.      Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Mode
        4. 8.2.2.4 Application Curves
        5. 8.2.2.5 Thermal Application
          1. 8.2.2.5.1 Power Dissipation
          2. 8.2.2.5.2 Conduction Loss
          3. 8.2.2.5.3 Switching Loss
          4. 8.2.2.5.4 Power Dissipation Due to Quiescent Current
          5. 8.2.2.5.5 Total Power Dissipation
          6. 8.2.2.5.6 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Pin Functions

PINI/OTYPEDESCRIPTION
NAMENO.
HTSSOPVQFN
AOUT14, 53OOutputWinding A output. Connect to stepper motor winding.
AOUT26, 74OOutputWinding A output. Connect to stepper motor winding.
PGND3, 122, 7—PowerPower ground. Connect to system ground.
BOUT28, 95OOutputWinding B output. Connect to stepper motor winding.
BOUT110, 116OOutputWinding B output. Connect to stepper motor winding.
CPH2823—PowerCharge pump switching node. Connect a X7R, 0.022-µF, VM-rated ceramic capacitor from CPH to CPL.
CPL2722
DIR2419IInputDirection input. Logic level sets the direction of stepping; internal pulldown resistor.
ENABLE2520IInputLogic low to disable device outputs; logic high to enable; internal pullup to DVDD. Also determines the type of OCP and OTSD response.
DVDD1510 — PowerLogic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
GND149—PowerDevice ground. Connect to system ground.
VREF1712IInputCurrent set reference input. Maximum value 3.3 V. DVDD can be used to provide VREF through a resistor divider.
M01813IInputMicrostepping mode-setting pins. Sets the step mode; internal pulldown resistor.
M12217
DECAY02116IInputDecay-mode setting pins. Sets the decay mode (see the Section 7.3.6 section).
DECAY12015
STEP2318IInputStep input. A rising edge causes the indexer to advance one step; internal pulldown resistor.
VCP124—PowerCharge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM.
VM2, 131, 8—PowerPower supply. Connect to motor supply voltage and bypass to PGND with two 0.01-µF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM.
TOFF1914IInputSets the Decay mode off time during current chopping; four level pin. Also sets the ripple current in smart tune ripple control mode.
nFAULT1611OOpen DrainFault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
nSLEEP2621IInputSleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. An nSLEEP low pulse clears faults.
PAD----Thermal pad. Connect to system ground.