SLVSAW4G July   2011  – December 2024 DRV8804

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Thermal Information
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Drivers
      2. 7.3.2 Serial Interface Operation
        1.       Daisy Chain Operation
      3. 7.3.3 nENBL and RESET Operation
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 Overcurrent Protection (OCP)
        2. 7.3.4.2 Thermal Shutdown (TSD)
        3. 7.3.4.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
      3. 8.2.3 Application Curves
    3.     Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance
    4. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
      3. 8.3.3 Thermal Considerations
        1. 8.3.3.1 Power Dissipation
        2. 8.3.3.2 Heatsinking
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Community Resources
    3. 9.3 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)(1)
MINNOMMAXUNIT
1tCYCClock cycle time62ns
2tCLKHClock high time25ns
3tCLKLClock low time25ns
4tSU(SDATIN)Setup time, SDATIN to SCLK5ns
5tH(SDATIN)Hold time, SDATIN to SCLK1ns
6tD(SDATOUT)Delay time, SCLK to SDATOUT, no external pullup resistor,
COUT = 100 pF		50100ns
7tW(LATCH)Pulse width, LATCH200ns
8tOE(ENABLE)Enable time, nENBL to output low60ns
9tD(LATCH)Delay time, LATCH to output change200ns
—tRESETRESET pulse width20µs
10tD(RESET)Reset delay before clock20µs
11tSTARTUPStart-up delay VM applied before clock55µs
(1) Not production tested.
DRV8804 DRV8804 Timing Requirements
More than 400 ns of delay should exist between the final SCLK rising edge and the LATCH rising edge. This ensures that the last data bit is shifted into the device properly.
Figure 6-1 DRV8804 Timing Requirements