SLVSAB2G May   2010  – December 2015 DRV8830


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation
      2. 7.3.2 Voltage Setting (VSET DAC)
      3. 7.3.3 Current Limit
      4. 7.3.4 Protection Circuits
        1. Overcurrent Protection (OCP)
        2. Thermal Shutdown (TSD)
        3. Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bridge Control
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 I2C Register Map
        1. REGISTER 0 - CONTROL
        2. REGISTER 1 - FAULT
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Motor Voltage
        2. Motor Current Trip Point
        3. Sense Resistor Selection
        4. Low Power Operation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supervisor
    2. 9.2 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The DRV8830 is an integrated motor driver solution used for brushed motor control. The device integrates one H-bridge, current regulation circuitry, and a PWM voltage regulation method.

Using the PWM voltage regulation allows the motor to maintain the desired speed as VCC changes. Battery operation is an example of using this feature. When the battery is new or fully charged VCC will be higher than when the battery is old or partially discharged. The speed of the motor will vary based on the voltage of the battery. By setting the desired voltage across the motor at a lower voltage, a fully charged battery will use less power and spin the motor at the same speed as a battery that has been partially discharged.

7.2 Functional Block Diagram

DRV8830 fbd_lvsab2.gif

7.3 Feature Description

7.3.1 Voltage Regulation

The DRV8830 provides the ability to regulate the voltage applied to the motor winding. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery.

The DRV8830 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.

The circuit monitors the voltage difference between the output pins and integrates it, to get an average DC voltage value. This voltage is divided by 4 and compared to the output voltage of the VSET DAC, which is set through the serial interface. If the averaged output voltage (divided by 4) is lower than VSET, the duty cycle of the PWM output is increased; if the averaged output voltage (divided by 4) is higher than VSET, the duty cycle is decreased.

During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. This is shown in Figure 8 as case 1. The current flow direction shown indicates the state when IN1 is high and IN2 is low.

Note that if the programmed output voltage is greater than the supply voltage, the device will operate at 100% duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional H-bridge driver.

During the PWM off time, winding current is recirculated by enabling both of the high-side FETs in the bridge. This is shown in Figure 8.

DRV8830 volt_reg2_lvsab2.gif Figure 8. Voltage Regulation

7.3.2 Voltage Setting (VSET DAC)

The DRV8830 includes an internal reference voltage that is connected to a DAC. This DAC generates a voltage which is used to set the PWM regulated output voltage as described in Voltage Regulation.

The DAC is controlled by the VSET bits from the serial interface. The commanded output voltage is shown in Table 1.

Table 1. Commanded Output Voltage

0x00h Reserved 0x20h 2.57
0x01h Reserved 0x21h 2.65
0x02h Reserved 0x22h 2.73
0x03h Reserved 0x23h 2.81
0x04h Reserved 0x24h 2.89
0x05h Reserved 0x25h 2.97
0x06h 0.48 0x26h 3.05
0x07h 0.56 0x27h 3.13
0x08h 0.64 0x28h 3.21
0x09h 0.72 0x29h 3.29
0x0Ah 0.80 0x2Ah 3.37
0x0Bh 0.88 0x2Bh 3.45
0x0Ch 0.96 0x2Ch 3.53
0x0Dh 1.04 0x2Dh 3.61
0x0Eh 1.12 0x2Eh 3.69
0x0Fh 1.20 0x2Fh 3.77
0x10h 1.29 0x30h 3.86
0x11h 1.37 0x31h 3.94
0x12h 1.45 0x32h 4.02
0x13h 1.53 0x33h 4.1
0x14h 1.61 0x34h 4.18
0x15h 1.69 0x35h 4.26
0x16h 1.77 0x36h 4.34
0x17h 1.85 0x37h 4.42
0x18h 1.93 0x38h 4.5
0x19h 2.01 0x39h 4.58
0x1Ah 2.09 0x3Ah 4.66
0x1Bh 2.17 0x3Bh 4.74
0x1Ch 2.25 0x3Ch 4.82
0x1Dh 2.33 0x3Dh 4.9
0x1Eh 2.41 0x3Eh 4.98
0x1Fh 2.49 0x3Fh 5.06

The voltage can be calculated as 4 x VREF x (VSET +1) / 64, where VREF is the internal 1.285-V reference.

7.3.3 Current Limit

A current limit circuit is provided to protect the system in the event of an overcurrent condition, such as what would be encountered if driving a DC motor at start-up or with an abnormal mechanical load (stall condition).

The motor current is sensed by monitoring the voltage across an external sense resistor. When the voltage exceeds a reference voltage of 200 mV for more than approximately 3 µs, the PWM duty cycle is reduced to limit the current through the motor to this value. This current limit allows for starting the motor while controlling the current.

If the current limit condition persists for some time, it is likely that a fault condition has been encountered, such as the motor being run into a stop or a stalled condition. An overcurrent event must persist for approximately
275 ms before the fault is registered. After approximately 275 ms, a fault signaled to the host by driving the FAULTn signal low and setting the FAULT and ILIMIT bits in the serial interface register. Operation of the motor driver will continue.

The current limit fault condition is cleared by setting both IN1 and IN2 to zero to disable the motor current, by putting the device into the shutdown state (IN1 and IN2 both set to 1), by setting the CLEAR bit in the fault register, or by removing and re-applying power to the device.

The resistor used to set the current limit must be less than 1 Ω. Its value may be calculated as follows:

Equation 1. DRV8830 eq1a_risense_lvsab2.gif


  • RISENSE is the current sense resistor value.
  • ILIMIT is the desired current limit (in mA).

If the current limit feature is not needed, the ISENSE pin may be directly connected to ground.

7.3.4 Protection Circuits

The DRV8830 is fully protected against undervoltage, overcurrent and overtemperature events. A FAULTn pin is available to signal a fault condition to the system, as well as a FAULT register in the serial interface that allows determination of the fault source. Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled, the FAULTn signal will be driven low, and the FAULT and OCP bits in the FAULT register will be set. The device will remain disabled until the CLEAR bit in the FAULT register is written to 1, or VCC is removed and re-applied.

Overcurrent conditions are sensed independently on both high and low side devices. A short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that OCP is independent of the current limit function, which is typically set to engage at a lower current level; the OCP function is intended to prevent damage to the device under abnormal (for example, short circuit) conditions. Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the FAULTn signal will be driven low, and the FAULT and OTS bits in the serial interface register will be set. Once the die temperature has fallen to a safe level operation will automatically resume. Undervoltage Lockout (UVLO)

If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all FETs in the H-bridge will be disabled, the FAULTn signal will be driven low, and the FAULT and UVLO bits in the FAULT register will be set. Operation will resume when VCC rises above the UVLO threshold.

Table 2. Device Protection

VCC undervoltage (UVLO) VCC < VUVLO FAULTn Disabled Disabled VCC > VUVLO
Overcurret (OCP) IOUT > IOCP FAULT n Disabled Operating Power cycle VCC
Thermal shutdown (TSD) TJ > TTSD FAULTn Disabled Operating TJ > TTSD – THYS

7.4 Device Functional Modes

The DRV8830 is active when either IN1 or IN2 are set to a logic high. Sleep mode is entered when both IN1 and IN2 are set to a logic low. When in sleep mode, the H-bridge FETs are disabled (Hi-Z).

Table 3. Modes of Operation

Operating IN1 or IN2 high Operating Operating
Sleep mode IN1 or IN2 low Disabled Diabled
Fault encountered Any fault condition met Disabled See Table 2

7.4.1 Bridge Control

The IN1 and IN2 control bits in the serial interface register enable the H-bridge outputs. Table 4 shows the logic:

Table 4. H-Bridge Logic

0 0 Z Z Standby / coast
0 1 L H Reverse
1 0 H L Forward
1 1 H H Brake

When both bits are zero, the output drivers are disabled and the device is placed into a low-power shutdown state. The current limit fault condition (if present) is also cleared.

At initial power up, the device will enter the low-power shutdown state. Note that when transitioning from either brake or standby mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to the commanded voltage. This can take up to 12 ms to go from standby to 100% duty cycle.

7.5 Programming

7.5.1 I2C-Compatible Serial Interface

The I2C interface allows control and monitoring of the DRV8830 by a microcontroller. I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C – Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.

A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer.

A slave device receives and/or transmits data on the bus under control of the master device. This device operates only as a slave device.

I2C communication is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while SCL is held high. After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W). After receiving a valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse.

The lower three bits of the device address are input from pins A0 - A1, which can be tied to VCC (logic high), GND (logic low), or left open. These three address bits are latched into the device at power up, so cannot be changed dynamically.

The upper address bits of the device address are fixed at 0xC0h, so the device address is as follows:

Table 5. Device Addresses

(as below)
0 0 0000 0xC0h 0xC1h
0 open 0001 0xC2h 0xC3h
0 1 0010 0xC4h 0xC5h
open 0 0011 0xC6h 0xC7h
open open 0100 0xC8h 0xC9h
open 1 0101 0xCAh 0xCBh
1 0 0110 0xCCh 0xCDh
1 open 0111 0xCEh 0xCFh
1 1 1000 0xD0h 0xD1h

The DRV8830 does not respond to the general call address.

A data byte follows the address acknowledge. If the R/W bit is low, the data is written from the master. If the R/W bit is high, the data from this device are the values read from the register previously selected by a write to the subaddress register. The data byte is followed by an acknowledge sent from this device. Data is output only if complete bytes are received and acknowledged. A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master to terminate the transfer.

A master bus device must wait at least 60 μs after power is applied to VCC to generate a START condition.

I2C transactions are shown in the timing diagrams Figure 9 and Figure 10:

DRV8830 i2c_read1_lvsab2.gif Figure 9. I2C Read Mode
DRV8830 i2c_write1_lvsab2.gif Figure 10. I2C Write Mode

7.6 Register Maps

7.6.1 I2C Register Map

Table 6. I2C Register Map

0 0x00 CONTROL 0x00h Sets state of outputs and output voltage
1 0x01 FAULT 0x00h Allows reading and clearing of fault conditions REGISTER 0 – CONTROL

The CONTROL register is used to set the state of the outputs as well as the DAC setting for the output voltage. The register is defined as follows:

Table 7. Register 0 – Control

D7 - D2 D1 D0
VSET[5..0] IN2 IN1
VSET[5..0]: Sets DAC output voltage. Refer to Voltage Setting above.
IN2: Along with IN1, sets state of outputs. Refer to Bridge Control above.
IN1: Along with IN2, sets state of outputs. Refer to Bridge Control above. REGISTER 1 – FAULT

The FAULT register is used to read the source of a fault condition, and to clear the status bits that indicated the fault. The register is defined as follows:

Table 8. Register 1 – Fault

D7 D6 - D5 D4 D3 D2 D1 D0
CLEAR: When written to 1, clears the fault status bits
ILIMIT: If set, indicates the fault was caused by an extended current limit event
OTS: If set, indicates that the fault was caused by an overtemperature (OTS) condition
UVLO: If set, indicates the fault was caused by an undervoltage lockout
OCP: If set, indicates the fault was caused by an overcurrent (OCP) event
FAULT: Set if any fault condition exists