SLVSGF5A May   2023  – December 2023 DRV8845

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Operating Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Motor Configurations
      2. 7.3.2 Stepper Control Logic
      3. 7.3.3 DC Motor Control
      4. 7.3.4 PWM Current Control
      5. 7.3.5 Current Regulation and Decay Mode
      6. 7.3.6 Blanking Time
      7. 7.3.7 Charge Pump
      8. 7.3.8 Logic-Level Pin Diagram
      9. 7.3.9 Protection Circuits
        1. 7.3.9.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.9.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.9.3 Overcurrent Protection (OCP)
        4. 7.3.9.4 Thermal Shutdown (OTSD)
        5. 7.3.9.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4. 7.4.4 Functional Modes Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Application Schematics
    3. 8.3 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Bulk Capacitance
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Stepper Control Logic

Control logic is implemented via the standard I0, I1, and PHASE interface. This logic allows for full, half, and quarter step modes. Each bridge also has an independent VREF input so that higher resolution step modes can be programmed by dynamically changing the voltage on the VREFx pins.

The PHASE inputs control the direction of current as shown in Table 7-2 -

Table 7-2 PHASE Truth Table

PHASEx

OUTxA

OUTxB

L

L

H

H

H

L

The I0x, I1x inputs control the current flowing through the outputs as shown in Table 7-3 -

Table 7-3 I0x, I1x Truth Table

I0x

I1x

Output Current

L

L

100%

H

L

67%

L

H

33%

H

H

0

The step sequencing table for full step, half sep and quarter step modes is shown in Table 7-4 -

Table 7-4 Step Sequencing Settings

Full

1/2

1/4

Phase 1 (%ITRIPMax)

I0x

I1x

PHASE

 Phase 2 (%ITRIPMax)

I0x

I1x

PHASE

1

1

0

H

H

X

100

L

L

0

2

33

L

H

1

100

L

L

0

1

2

3

100/67*

L/H*

L

1

100/67*

L/H*

L

0

4

100

L

L

1

33

L

H

0

3

5

100

L

L

1

0

H

H

X

6

100

L

L

1

33

L

H

1

2

4

7

100/67*

L/H*

L

1

100/67*

L/H*

L

1

8

33

L

H

1

100

L

L

1

5

9

0

H

H

X

100

L

L

1

10

33

L

H

0

100

L

L

1

3

6

11

100/67*

L/H*

L

0

100/67*

L/H*

L

1

12

100

L

L

0

33

L

H

1

7

13

100

L

L

0

0

H

H

X

14

100

L

L

0

33

L

H

0

4

8

15

100/67*

L/H*

L

0

100/67*

L/H*

L

0

16

33

L

H

0

100

L

L

0
GUID-20230418-SS0I-MXFV-06C2-1VPB4JNFBPCK-low.svg Figure 7-2 Step Sequencing for Full-Step Increments
GUID-20230418-SS0I-XTNH-3S27-CDFPDBVXZJPX-low.svg Figure 7-3 Step Sequencing for Half-Step Increments
GUID-20230418-SS0I-D1LP-DZQ9-LGQCFXNJRWST-low.svg Figure 7-4 Step Sequence for Quarter-Step Increments