SNLS399B January 2012 – January 2015 DS100DF410
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DS100DF410 can be configured by the user to optimize its operation. The four channels can be optimized independently in SMBus master or SMBus slave mode. The operational settings available for user configuration include the following.
Configuration of the DS100DF410 is accomplished by writing the appropriate values into various device registers over the SMBus. This can either be done while the device is operating or upon initial power-up. When the DS100DF410 is operating it behaves like an SMBus slave device, and its register contents can be read or written over the SMBus. Optionally, when the DS100DF410 first powers up, it can behave like an SMBus master and read its register contents autonomously from an external EEPROM.
This section lists some critical areas for high speed printed circuit board design consideration and study.
To begin the design process, determine the following:
Figure 7 shows a typical output eye diagram for the DS100DF410 operating at 10.3125 Gbps with default VOD of 600mVp-p and de-emphasis setting of -2dB.
Figure 8 shows an example of Tx de-emphasis for a DS100DF410 operating at 10.3125 Gbps. In this example, the high speed output is configured for 600mVp-p VOD and de-emphasis is set to -4.5dB. An 8T pattern is used to evaluate the driver, which consists of 0xFF00.