SNLS430C October   2012  – August 2014 DS125BR111

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics — Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Functional Datapath Blocks
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
      3. 8.4.3 Signal Conditioning Settings
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 Transfer Of Data Via The SMBus
      2. 8.6.2 SMBus Transactions
      3. 8.6.3 Writing a Register
      4. 8.6.4 Reading a Register
      5. 8.6.5 SMBus Register Information
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Signal Integrity
      2. 9.1.2 RX-Detect in SAS/SATA Applications
      3. 9.1.3 PCIe Applications
        1. 9.1.3.1 RXDET When Using SMBus Modes
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The DS125BR111 pinout promotes makes for easy high speed routing and layout. To optimize DS125BR111 performance refer to the following guidelines;

  1. Differential pairs going into or out of the DS125BR111 should have adequate pair - pair spacing to minimize crosstalk. Keep a 5x spacing ratio as shown on the Blue pairs in the layout example.
  2. Place local VIN and VDD capacitors as close as possible to the device supply pins to ensure a low inductance layout. Often the best location is directly under the DS125BR111 pins.
  3. Use return current via connections to link reference planes locally. This ensures a low inductance return current path when the differential signal changes layers.
  4. Open up the supply planes around differential vias to better match the trace impedance.
  5. Place GND vias around the DAP perimeter to ensure optimal electrical and thermal performance.
  6. Use 0201 body size coupling capacitors whenever possible, 0402 body size capacitors can also be used if they are placed closer to the Rx on the channel.

11.2 Layout Example

In most cases DS125BR111 layouts will fit neatly into a single or 1-lane application. The example layout shows how to "flip" one of the DS125BR111 channels to produce a 2-channel unidirectional layout.

111layout.gifFigure 12. DS125BR111 Example Unidirectional Layout