SNLS419D July   2012  – May 2015 DS125BR401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Electrical Characteristics — Serial Management Bus Interface
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Typical 4-Level Input Thresholds
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pin Control Mode
      2. 9.4.2 SMBUS Mode
    5. 9.5 Programming
      1. 9.5.1 PCIe Signal Integrity
        1. 9.5.1.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
          1. 9.5.1.1.1 Signal Detect Control for Datarates Above 8 Gbps
        2. 9.5.1.2 MODE Operation With SMBus Registers
      2. 9.5.2 SMBUS Master Mode
      3. 9.5.3 System Management Bus (SMBus) and Configuration Registers
        1. 9.5.3.1 Transfer of Data Through the SMBus
        2. 9.5.3.2 SMBus Transactions
        3. 9.5.3.3 Writing a Register
        4. 9.5.3.4 Reading a Register
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 3.3-V or 2.5-V Supply Mode Operation
    2. 11.2 Power Supply Bypassing
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Layout Considerations for Differential Pairs
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Description (continued)

When operating in 10G-KR, and PCIe Gen-3 mode, the DS125BR401 allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This transparency to the link training protocol can extend the maximum channel loss with minimum latency. With a low power consumption of 65 mW/channel (typical) and the option to turn off unused channels, the DS125BR401 enables energy efficient system design. A single supply of 3.3 V or 2.5 V is required to power the device.

The programmable settings can be applied easily through pins, software (SMBus or I2C), or loaded through an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.