SNLS419D July   2012  – May 2015 DS125BR401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Electrical Characteristics — Serial Management Bus Interface
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Typical 4-Level Input Thresholds
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pin Control Mode
      2. 9.4.2 SMBUS Mode
    5. 9.5 Programming
      1. 9.5.1 PCIe Signal Integrity
        1. 9.5.1.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
          1. 9.5.1.1.1 Signal Detect Control for Datarates Above 8 Gbps
        2. 9.5.1.2 MODE Operation With SMBus Registers
      2. 9.5.2 SMBUS Master Mode
      3. 9.5.3 System Management Bus (SMBus) and Configuration Registers
        1. 9.5.3.1 Transfer of Data Through the SMBus
        2. 9.5.3.2 SMBus Transactions
        3. 9.5.3.3 Writing a Register
        4. 9.5.3.4 Reading a Register
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 3.3-V or 2.5-V Supply Mode Operation
    2. 11.2 Power Supply Bypassing
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Layout Considerations for Differential Pairs
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

NJY Package
54-Pin WQFN
Top View
DS125BR401 30198792.gif

Pin Functions(1)

PIN I/O, TYPE DESCRIPTION
NAME NUMBER
DIFFERENTIAL HIGH-SPEED I/Os
INB_0+, INB_0-, INB_1+, INB_1-, INB_2+, INB_2-, INB_3+, INB_3- 45, 44, 43, 42
40, 39, 38, 37		 I Inverting and noninverting CML differential inputs to the equalizer. On-chip 50-Ω termination resistor connects INB_n+ to VDD and INB_n- to VDD when enabled.
AC coupling required on high-speed I/O
OUTB_0+, OUTB_0-, OUTB_1+, OUTB_1-, OUTB_2+, OUTB_2-, OUTB_3+, OUTB_3- 1, 2, 3, 4
5, 6, 7, 8		 O Inverting and noninverting 50-Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
INA_0+, INA_0-, INA_1+, INA_1-, INA_2+, INA_2-, INA_3+, INA_3- 10, 11, 12, 13
15, 16, 17, 18		 I Inverting and noninverting CML differential inputs to the equalizer. On-chip 50-Ω termination resistor connects INA_n+ to VDD and INA_n- to VDD when enabled.
AC coupling required on high-speed I/O
OUTA_0+, OUTA_0-, OUTA_1+, OUTA_1-, OUTA_2+, OUTA_2-, OUTA_3+, OUTA_3- 35, 34, 33, 32
31, 30, 29, 28		 O Inverting and noninverting 50-Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
CONTROL PINS — SHARED (LVCMOS)
ENSMB 48 I, 4-LEVEL,
LVCMOS		 System Management Bus (SMBus) Enable pin
Tie 1 kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1 kΩ to GND = Pin Mode
ENSMB = 1 (SMBUS MODE)
SCL 50 I, 2-LEVEL, LVCMOS,
O, OPEN Drain		 ENSMB Master or Slave mode
SMBUS clock input pin is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
SDA 49 I, 2-LEVEL, LVCMOS,
O, OPEN Drain		 ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open-drain (pulldown only) output.
AD0-AD3 54, 53, 47, 46 I, 4-LEVEL, LVCMOS ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus slave address inputs.
There are 16 addresses supported by these pins. Pins must be tied LOW or HIGH when used to define the device SMBus address.
READ_EN 26 I, 2-LEVEL, LVCMOS When using an External EEPROM, a transition from high to low starts the load from the external EEPROM
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1		 20, 19
46, 47		 I, 4-LEVEL,
LVCMOS 		EQA[1:0] and EQB[1:0] control the level of equalization of the A/B sides as shown in . The pins are active only when ENSMB is deasserted (low). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane. The EQB[1:0] pins are converted to SMBUS AD2, AD3 inputs. See Table 2.
DEMA0, DEMA1
DEMB0, DEMB1		 49, 50
53, 54		 I, 4-LEVEL,
LVCMOS		 DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the A/B sides as shown in . The pins are only active when ENSMB is deasserted (low). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane. The DEMA[1:0] pins are converted to SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs. See Table 3.
MODE 21 I, 4-LEVEL,
LVCMOS 		MODE control pin selects operating modes.
Tie 1 kΩ to GND = PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to
6 Gbps)
FLOAT = AUTO Rate Select (for PCIe)
Tie 20 kΩ to GND = PCIe Gen-3 without De-emphasis
Tie 1 kΩ to VDD = 10G-KR
See Table 6
SD_TH 26 I, 4-LEVEL,
LVCMOS 		Controls the internal Signal Detect Threshold.
For datarates above 8 Gbps the Signal Detect function should be disabled to avoid potential for intermittent data loss. See Table 5.
CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS)
RXDET 22 I, 4-LEVEL,
LVCMOS 		The RXDET pin controls the receiver detect function. Depending on the input level, a 50 Ω or >50 kΩ termination to the power rail is enabled.
See Table 4.
LPBK 23 I, 4-LEVEL,
LVCMOS 		Controls the loopback function
Tie 1 kΩ to GND = Root Complex Loopback (INA_n to OUTB_n)
Float = Normal Operation
Tie 1 kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
VDD_SEL 25 I, LVCMOS Controls the internal regulator
Float = 2.5-V mode
Tie GND = 3.3-V mode
PWDN 52 I, LVCMOS Tie High = Low power - power down
Tie GND = Normal Operation
See Table 4.
ALL_DONE 27 O, LVCMOS Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
POWER
VIN 24 Power In 3.3-V mode, feed 3.3 V to VIN
In 2.5-V mode, leave floating.
VDD 9, 14,36, 41, 51 Power Power supply pins CML/analog
2.5-V mode, connect to 2.5 V
3.3-V mode, connect 0.1-µF capacitor to each VDD pin
GND DAP Power Ground pad (DAP - die attach pad). See Power Supply Recommendations for proper power supply decoupling.
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
For 2.5-V mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.