SNLS491B July 2014 – February 2015 DS125BR820
Two approaches are recommended to ensure that the DS125BR820 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the DS125BR820. Smaller body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
The DS125BR820 has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3 V mode operation, the VIN pin = 3.3 V is used to supply power to the device. The internal regulator then provides the 2.5 V to the VDD pins of the device and a 0.1 μF cap is needed at each of the five VDD pins for power supply de-coupling (total capacitance should equal 0.5 μF). The VDD_SEL pin must be tied to GND to enable the internal regulator. In 2.5 V mode operation, the VIN pin should be left open and 2.5 V supply must be applied to the five VDD pins to power the device. The VDD_SEL pin must be left open (no connect) to disable the internal regulator.