SNLS645A August   2019  – December 2019 DS160PR410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 SMBUS/I2C Timing Charateristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Slave Mode
TSDA-HD Data hold time 0 ns
TSDA-SU Data setup time 100 ns
TSDA-R SDA rise time, read operation Pull-up resistor = 1 kΩ, Cb = 50 pF 120 ns
TSDA-F SDA fall time, read operation Pull-up resistor = 1 kΩ, Cb = 50 pF 10 ns
Master Mode
fSCL-M SCL clock frequency EN_SMB = L3 (Master Mode) 220 300 365 kHz
TSCL-LOW-M SCL low period 1.58 2.0 2.62 µs
TSCL-HIGH-M SCL high period 1.15 1.40 1.8 µs
THD-START-M Hold time start operation 1.5 µs
TSU-START-M Setup time start operation 1.5 µs
TSDA-HD-M Data hold time 0.9 µs
TSDA-SU-M Data setup time 1.3 µs
TSU-STOP-M Stop condition setup time 1.5 µs
TBUF-M Bus free time between Stop-Start 2.6 µs
TSDC-R-M SCL rise time Pull-up resistor = 1 kΩ 120 ns
TSDC-F-M SCL fall time Pull-up resistor = 1 kΩ 10 ns
EEPROM Timing
TEEPROM EEPROM configuration load time Time to assert ALL_DONE_N after READ_EN_N has been asserted. Single device reading its configuration from an EEPROM with common channel configuration. This time scales with the number of devices reading from the same EEPROM. Does not include power-on reset time. 1 ms
TPOR Time to first SMBus access Power supply stable after initial ramp. Includes initial power-on reset time. 26 ms