SNLS658 December   2020 DS160PR810


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. Pin Mode
          1. Four-Level Control Inputs
        2. SMBUS/I2C Register Control Interface
        3. SMBus/I 2 C Master Mode Configuration (EEPROM Self Load)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x16 Lane Configuration
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

SMBus/I2C Master Mode Configuration (EEPROM Self Load)

The DS160PR810 can also be configured by reading from EEPROM. To enter into this mode MODE pin must be set to L1. The EEPROM load operation only happens once after device's initial power-up. If the device is configured for SMBus master mode, it will remain in the SMBus IDLE state until the READ_EN_N pin is asserted to LOW. After the READ_EN_N pin is driven LOW, the device becomes an SMBus master and attempts to self-configure by reading device settings stored in an external EEPROM (SMBus 8-bit address 0xA0). When the device has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW. SMBus/I2C slave operation is available in this mode before, during or after EEPROM reading. Note during EEPROM reading if the external SMBus/I2C master wants to access the device registers it must support arbitration. Refer to the Understanding EEPROM Programming for PCI-Express 4.0 Redrivers (SNLA342) application report for more information.

When designing a system for using the external EEPROM, the user must follow these specific guidelines:

  • EEPROM size of 2 kb (256 × 8-bit) is recommended.
  • Set MODE = L1, configure for SMBus master mode
  • The external EEPROM device address byte must be 0xA0 and capable of 400 kHz operation at 3.3 V supply
  • In SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 10 pF.

Figure 7-1 shows a use case with four DS160PR810 to implement a PCIe x16 configuration, but the user can cascade any number of DS160PR810 devices in a similar way. Tie first device’s READ_EN_N pin low to automatically initiate EEPROM read at power up. Alternately the READ_EN_N pin of the first device can also be controlled by a microcontroller to initiate the EEPROM read manually. Leave the final device’s ALL_DONE_N pin floating, or connect the pin to a microcontroller input to monitor the completion of the final EEPROM read.

GUID-BC019F1E-F8A3-460A-A5E7-6D2775CF03FA-low.gif Figure 7-1 Daisy Chain Four DS160PR810 Devices to Read from Single EEPROM