SNLS680 December   2020 DS160UP822

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I 2 C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI 2x2 Cross Point Mux for x24 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 SMBUS/I2C Timing Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Slave Mode
tSP Pulse width of spikes which must be
suppressed by the input filter		 50 ns
tHD-STA Hold time (repeated) START condition.
After this period, the first clock pulse is
generated		 0.6 µs
tLOW LOW period of the SCL clock 1.3 µs
THIGH HIGH period of the SCL clock 0.6 µs
tSU-STA Set-up time for a repeated START
condition		 0.6 µs
tHD-DAT Data hold time 0 µs
tSU-DAT Data setup time 0.1 µs
tr Rise time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10pF 120 ns
tf Fall time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10pF 2 ns
tSU-STO Set-up time for STOP condition 0.6 µs
tBUF Bus free time between a STOP and
START condition		 1.3 µs
tVD-DAT Data valid time 0.9 µs
tVD-ACK Data valid acknowledge time 0.9 µs
Cb capacitive load for each bus line 400 pF
Master Mode
fSCL-M SCL clock frequency MODE = L1 (Master Mode) 303 kHz
tLOW-M SCL low period 1.9 µs
tHIGH-M SCL high period 1.4 µs
tSU-STA-M Set-up time for a repeated START
condition		 2 µs
tHD-STA-M Hold time (repeated) START condition.
After this period, the first clock pulse is
generated		 1.5 µs
tSU-DAT-M Data setup time 1.4 µs
tHD-DAT-M Data hold time 0.5 µs
tR-M Rise time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10pF 120 ns
tF-M Fall time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10pF 2 ns
tSU-STO-M Stop condition setup time 1.5 µs
EEPROM Timing
TEEPROM EEPROM configuration load time Time to assert ALL_DONE_N after READ_EN_N has been asserted. Single device reading its configuration from an EEPROM with common channel configuration with individual channel settings. This time scales with the number of devices reading from the same EEPROM. Does not include power-on reset time. 7.5 ms
TPOR Time to first SMBus access Power supply stable after initial ramp. Includes initial power-on reset time. 50 ms