SNLS739 October   2023 DS320PR410

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNQ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2.2 Channel Registers

Table 7-9 RX Detect Status Register (Channel Register Base + Offset = 0x00)
BitFieldTypeResetDescription
7rx_det_comp_pR0x0Rx Detect positive data pin status:

0: Not detected

1: Detected – the value is latched

6rx_det_comp_nR0x0Rx Detect negative data pin status:

0: Not detected

1: Detected – the value is latched

5-0RESERVEDR0x0Reserved
Table 7-10 EQ Gain Control Register (Channel Register Base + Offset = 0x01)
BitFieldTypeResetDescription
7eq_stage1_bypassR/W0x0

Enable EQ stage 1 bypass:

0: Bypass disabled

1: Bypass enabled

6eq_stage1_3R/W0x0

EQ Boost stage 1 control

See Table 7-1 for details

5eq_stage1_2R/W0x0
4eq_stage1_1R/W0x0
3eq_stage1_0R/W0x0
2eq_stage2_2R/W0x0

EQ Boost stage 2 control

See Table 7-1 for details

1eq_stage2_1R/W0x0
0eq_stage2_0R/W0x0
Table 7-11 EQ Gain / Flat Gain Control Register (Channel Register Base + Offset = 0x03)
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6eq_profile_3R/W0x0

EQ mid-frequency boost profile

See Table 7-1 for details

5eq_profile_2R/W0x0
4eq_profile_1R/W0x0
3eq_profile_0R/W0x0
2flat_gain_2R/W0x1

Flat gain select:

See Table 7-2 for details

1flat_gain_1R/W0x0
0flat_gain_0R/W0x1
Table 7-12 RX Detect Control Register (Channel Register Base + Offset = 0x04)
BitFieldTypeResetDescription
7-3RESERVEDR0x0Reserved
2mr_rx_det_manR/W0x0

Manual override of rx_detect_p/n decision:

0: rx detect state machine is enabled

1: rx detect state machine is overridden – always valid RX termination detected

1en_rx_det_countR/W0x0Enable additional RX detect polling

0: Additional RX detect polling disabled

1: Additional RX detect polling enabled

0sel_rx_det_countR/W0x0

Select number of valid RX detect polls – gated by en_rx_det_count = 1

0: Device transmitters poll until 2 consecutive valid detections

1: Device transmitters poll until 3 consecutive valid detections

Table 7-13 PD Override Register (Channel Register Base + Offset = 0x05)
BitFieldTypeResetDescription
7device_en_overrideR/W0x0Enable power down overrides through SMBus/I2C

0: Manual override disabled

1: Manual override enabled

6-0device_enR/W0x1111111Manual power down of redriver various blocks – gated by device_en_override = 1

1111111: All blocks are enabled

0000000: All blocks are disabled

Table 7-14 Bias Register (Channel Register Base + Offset = 0x06)
BitFieldTypeResetDescription
5-3Bias currentR/W0x100Control bias current

Set 001 for best performance

7,6,2-0ReservedR/W0x00000Reserved