SNLS739 October   2023 DS320PR410

PRODUCTION DATA  

1.   1
2. 1 Features
3. 2 Applications
4. 3 Description
5. 4 Revision History
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 DC Electrical Characteristics
   6. 6.6 High Speed Electrical Characteristics
   7. 6.7 SMBUS/I2C Timing Charateristics
   8. 6.8 Typical Characteristics
   9. 6.9 Typical Jitter Characteristics
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
   4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
   5. 7.5 Programming
      1. 7.5.1 Pin mode
         1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
         1. 7.5.2.1 Shared Registers
         2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
9. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
         1. 8.2.1.1 Design Requirements
         2. 8.2.1.2 Detailed Design Procedure
         3. 8.2.1.3 Application Curves
   3. 8.3 Power Supply Recommendations
   4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
11. 10Mechanical, Packaging, and Orderable Information