SNLS344G July   2011  – August 2015 DS80PCI102

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Electrical Characteristics — Serial Management Bus Interface
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Guidelines
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode
      2. 7.4.2 SMBUS Mode
    5. 7.5 Programming
      1. 7.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 7.5.2 Transfer of Data Through the SMBus
      3. 7.5.3 SMBus Transactions
      4. 7.5.4 Writing a Register
      5. 7.5.5 Reading a Register
      6. 7.5.6 EEPROM Programming
        1. 7.5.6.1 Master EEPROM Programming
        2. 7.5.6.2 EEPROM Address Mapping
    6. 7.6 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 3.3-V or 2.5-V Supply Mode Operation
    2. 9.2 Power Supply Bypass
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The DS80PCI102 provides input CTLE and output De-emphasis equalization for lossy printed circuit board trace and cables. The DS80PCI102 operates in three modes: Pin Control Mode configuration (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) for register configurations from host controller or SMBus Master Mode (ENSMB = Float) for loading the register configurations from an external EEPROM.

7.2 Functional Block Diagram

DS80PCI102 ds80pci102_block_diagram.gif

7.3 Feature Description

7.3.1 4-Level Input Configuration Guidelines

The 4-level input pins use a resistor divider to help set the four valid levels. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the package pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level. Using the 1-kΩ pullup, 1-kΩ pulldown, no connect, or 20-kΩ pulldown provide the optimal voltage levels for each of the four input states.

Table 1. 4-Level Input Voltage

LEVEL SETTING 3.3-V MODE 2.5-V MODE
0 1 kΩ to GND 0.1 V 0.08 V
R 20 kΩ to GND 0.33 × VIN 0.33 × VDD
F FLOAT 0.67 × VIN 0.67 × VDD
1 1 kΩ to VDD/VIN VIN – 0.05 V VDD – 0.04 V

Typical 4-level input thresholds:

  • Level 1 to 2 = 0.2 VIN or VDD
  • Level 2 to 3 = 0.5 VIN or VDD
  • Level 3 to 4 = 0.8 VIN or VDD

To minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and pulldown resistors are recommended. If several 4-level inputs require the same setting, it is possible to combine two or more 1-kΩ resistors into a single lower value resistor. As an example; combining two inputs with a single 500-Ω resistor is a good way to save board space. For the 20 kΩ to GND, this should also scale to 10 kΩ.

Table 2. Equalizer Settings(1)

LEVEL EQA1
EQB1
EQA0
EQB0
EQ – 8 BITS [7:0] dB at
1.25 GHz
dB at
2.5 GHz
dB at
4 GHz
SUGGESTED USE
1 0 0 0000 0000 = 0x00 2.1 3.7 4.9 FR4 < 5 inch trace
2 0 R 0000 0001 = 0x01 3.4 5.8 7.9 FR4 5 inch 5–mil trace
3 0 Float 0000 0010 = 0x02 4.8 7.7 9.9 FR4 5 inch 4–mil trace
4 0 1 0000 0011 = 0x03 5.9 8.9 11.0 FR4 10 inch 5–mil trace
5 R 0 0000 0111 = 0x07 7.2 11.2 14.3 FR4 10 inch 4–mil trace
6 R R 0001 0101 = 0x15 6.1 11.4 14.6 FR4 15 inch 4–mil trace
7 R Float 0000 1011 = 0x0B 8.8 13.5 17.0 FR4 20 inch 4–mil trace
8 R 1 0000 1111 = 0x0F 10.2 15.0 18.5 FR4 25 to 30 inch 4–mil trace
9 Float 0 0101 0101 = 0x55 7.5 12.8 18.0 FR4 30 inch 4–mil trace
10 Float R 0001 1111 = 0x1F 11.4 17.4 22.0 FR4 35 inch 4–mil trace
11 Float Float 0010 1111 = 0x2F 13.0 19.7 24.4 10 m, 30-awg cable
12 Float 1 0011 1111 = 0x3F 14.2 21.1 25.8 10 m – 12 m cable
13 1 0 1010 1010 = 0xAA 13.8 21.7 27.4
14 1 R 0111 1111 = 0x7F 15.6 23.5 29.0
15 1 Float 1011 1111 = 0xBF 17.2 25.8 31.4
16 1 1 1111 1111 = 0xFF 18.4 27.3 32.7
(1) The suggested equalizer CTLE settings are based on 0 dB of TX preshoot/de-emphasis. In PCIe Gen 3 applications which use TX preshoot/de-emphasis, the CTLE should be set to a lower boost setting to optimize the RX eye opening.

Table 3. Output Voltage and De-Emphasis Settings

LEVEL VOD_SEL DEMA
DEMB
VOD (Vp-p) DEM (dB)(1) SUGGESTED USE
1 0 0 0.7 0 FR4 < 5 inch 4–mil trace
2 0 R 0.7 - 6 FR4 12 inch 4–mil trace
3 0 Float 0.7 - 3.5 FR4 10 inch 4–mil trace
4 0 1 0.7 - 9 FR4 15 inch 4–mil trace
5 R 0 1.2 0 FR4 < 5 inch 4–mil trace
6 R R 1.2 - 6 FR4 12 inch 4–mil trace
7 R Float 1.2 - 3.5 FR4 10 inch 4–mil trace
8 R 1 1.2 - 9 FR4 15 inch 4–mil trace
9 Float 0 1.0 0 FR4 < 5 inch 4–mil trace
10 Float R 1.0 - 6 FR4 15 inch 4–mil trace
11 Float Float 1.0 - 3.5 FR4 10 inch 4–mil trace
12 Float 1 1.0 - 9 FR4 20 inch 4–mil trace
13 1 0 1.1 0 FR4 < 5 inch 4–mil trace
14 1 R 1.1 - 1.5 FR4 5 inch 4–mil trace
15 1 Float 1.3 - 1.5 FR4 5 inch 4–mil trace
16 1 1 1.3 - 3.5 FR4 10 inch 4–mil trace
(1) The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are available in GEN1, GEN2, and GEN 3 modes when RATE = Float.

Table 4. RX-Detect Settings

PRSNT(1)
(PIN 52)
RXDET
(PIN 22)
SMBus REG
BIT[3:2]
INPUT TERMINATION COMMENTS
0 0 00 Hi-Z Manual RX-Detect, input is high-impedance mode
0 Tie 20 kΩ
to GND
01 Pre Detect: Hi-Z
Post Detect: 50 Ω
Auto RX-Detect, outputs test every 12 ms for 600 ms then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
Reset function by pulsing PRSNT high for 5 µs then low again
0 Float
(Default)
10 Pre Detect: Hi-Z
Post Detect: 50 Ω
Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
Reset function by pulsing PRSNT high for 5 µs then low again
0 1 11 50 Ω Manual RX-Detect, input is 50 Ω
1 X Hi-Z Power-down mode, input is high impedance, output drivers are disabled

Used to reset RX-Detect State Machine when held high for 5 µs

(1) In SMBus Slave Mode, the Rx Detect State Machine can be manually reset in software by overriding the device PRSNT function. This is accomplished by setting the Override RXDET bit (Reg 0x02[7]) and then toggling the RXDET Value bit (Reg 0x02[6]). See Table 10 for more information about resetting the Rx Detect State Machine.

Table 5. Signal Detect Threshold Level(1)

SD_TH SMBus REG BIT [3:2] AND [1:0] ASSERT LEVEL (TYP) DEASSERT LEVEL (TYP)
0 10 210 mVp-p 150 mVp-p
R 01 160 mVp-p 100 mVp-p
F (default) 00 180 mVp-p 110 mVp-p
1 11 190 mVp-p 130 mVp-p
(1) VDD = 2.5 V, 25°C, and 0101 pattern at 8 Gbps.

7.4 Device Functional Modes

The DS80PCI102 is a low power media compensation 1 lane repeater optimized for PCI Express Gen 1/2 and 3. The DS80PCI102 compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The DS80PCI102 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB = float) to load register information from external EEPROM; refer to Table 8 for additional information.

7.4.1 Pin Control Mode

When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically adjusted per the De- Emphasis table below. The RXDET pins provides automatic and manual control for input termination (50 Ω or > 50 kΩ). RATE setting is also pin controllable with pin selections (Gen 1/2, auto detect and Gen 3). The receiver electrical idle detect threshold is also adjustable through the SD_TH pin.

7.4.2 SMBUS Mode

When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (RATE, RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is driven low all registers are reset to their default state. If PRSNT is asserted while ENSMB is high, the registers retain their current state.

Equalization settings accessible through the pin controls were chosen to meet the needs of most PCIe applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the SMBus registers. Each input has a total of 256 possible equalization settings. The 4-Level Input Configuration Guidelines show the 16 setting when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-emphasis levels are set by registers.

7.5 Programming

7.5.1 System Management Bus (SMBus) and Configuration Registers

The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ to VDD to enable SMBus slave mode and allow access to the configuration registers.

The DS80PCI102 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device default address byte is 0xB0. Based on the SMBus 2.0 specification, the DS80PCI102 has a 7-bit slave address. The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the AD[3:0] inputs. Below are the 16 addresses.

Table 6. Device Slave Address Bytes

AD[3:0] SETTINGS ADDRESS BYTES (HEX) 7-BIT SLAVE ADDRESS (HEX)
0000 B0 58
0001 B2 59
0010 B4 5A
0011 B6 5B
0100 B8 5C
0101 BA 5D
0110 BC 5E
0111 BE 5F
1000 C0 60
1001 C2 61
1010 C4 62
1011 C6 63
1100 C8 64
1101 CA 65
1110 CC 66
1111 CE 67

The SDA/SCL pins are 3.3-V tolerant, but are not 5-V tolerant. An external pullup resistor is required on the SDA and SCL line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading, and speed.

7.5.2 Transfer of Data Through the SMBus

During normal operation the data on SDA must be stable during the time when SCL is High.

There are three unique states for the SMBus:

START: A high-to-low transition on SDA while SCL is High indicates a message START condition.

STOP: A low-to-high transition on SDA while SCL is High indicates a message STOP condition.

IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.

7.5.3 SMBus Transactions

The device supports WRITE and READ transactions. See Table 10 for register address, type (Read/Write, Read Only), default value and function information.

7.5.4 Writing a Register

To write a register, the following protocol is used (see SMBus 2.0 specification).

  1. The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
  2. The Device (Slave) drives the ACK bit (0).
  3. The Host drives the 8-bit Register Address.
  4. The Device drives an ACK bit (0).
  5. The Host drive the 8-bit data byte.
  6. The Device drives an ACK bit (0).
  7. The Host drives a STOP condition.

The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur.

7.5.5 Reading a Register

To read a register, the following protocol is used (see SMBus 2.0 specification).

  1. The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
  2. The Device (Slave) drives the ACK bit (0).
  3. The Host drives the 8-bit Register Address.
  4. The Device drives an ACK bit (0).
  5. The Host drives a START condition.
  6. The Host drives the 7-bit SMBus Address, and a 1 indicating a READ.
  7. The Device drives an ACK bit 0.
  8. The Device drives the 8-bit data value (register contents).
  9. The Host drives a NACK bit 1 indicating end of the READ transfer.
  10. The Host drives a STOP condition.

The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur.

See Table 10 for more information.

DS80PCI102 30156905.gifFigure 7. Typical SMBus Write Operation

7.5.6 EEPROM Programming

The DS80PCI102 supports reading directly from an external EEPROM device by implementing SMBus Master mode. When using the SMBus master mode, the DS80PCI102 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the following guidelines should be followed:

  • Set the DS80PCI102 into SMBus Master Mode.
    • ENSMB (PIN 3) = Float
  • The external EEPROM device must support 1-MHz operation.
  • The external EEPROM device address byte must be 0xA0.
  • Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.
  • The device address can be set with the use of the AD[3:0] input up to 16 different addresses. Use the example below to set each of the SMBus addresses.
    • AD[3:0] = 0001'b, the device address byte is 0xB2
    • AD[3:0] = 0010'b, the device address byte is 0xB4
    • AD[3:0] = 0011'b, the device address byte is 0xB6
    • AD[3:0] = 0100'b, the device address byte is 0xB8
  • The master implementation in the DS80PCI102 supports multiple devices reading from one EEPROM. When tying multiple devices to the SDA and SCL pins, use these guidelines:
    • Use adjacent SMBus addresses for the 4 devices
    • Use a pullup resistor on SDA; value = 4.7 kΩ
    • Use a pullup resistor on SCL; value = 4.7 kΩ
    • Daisy-chain READEN (Pin 17) and DONE (Pin18) from one device to the next device in the sequence.
      1. Tie READEN of the first device in the chain (U1) to GND
      2. Tie DONE of U1 to READEN of U2
      3. Tie DONE of U2 to READEN of U3
      4. Tie DONE of U3 to READEN of U4
      5. Optional: Tie DONE of U4 to a LED to show each of the devices have been loaded successfully

7.5.6.1 Master EEPROM Programming

The following example represents a 2 kbits (256 × 8-bit) EEPROM in hex format for the DS80PCI102 device. The first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all devices connected to the same SMBus line. There is a CRC enable flag to enable or disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the MAP bit is not present, the configuration data start address immediately follows the 3-byte base header. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM. There are 37 bytes of data size for each DS80PCI102 device. For more details about EEPROM programming and Master mode, refer to SNLA228.

DS80PCI102 30156915.gifFigure 8. Typical EEPROM Data Set

NOTE

The maximum EEPROM size supported is 8kbits (1024 × 8 bits).

The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the DS80PCI102, or 40 bytes in total. The result of this calculation is placed immediately after the DS80PCI102 data in the EEPROM, which ends with "5454". The CRC-8 in the DS80PCI102 uses a polynomial = x8 + x2 + x + 1.

There are two pins that provide unique functions in SMBus Master mode:

  • DONE
  • READEN

When the DS80PCI102 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the READEN pin goes low. When the DS80PCI102 is finished reading its configuration from the external EEPROM, it drives the DONE pin low. In applications where there is more than one DS80PCI102 on the same SMBus, bus contention can result if more than one DS80PCI102 tries to take control of the SMBus at the same time. The READEN and DONE pins prevent this bus contention. The system should be designed so that the READEN pin from one DS80PCI102 in the system is driven low on power-up. This DS80PCI102 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is finished reading its configuration, it will drive the DONE pin low. This pin should be connected to the READEN pin of another DS80PCI102. When this second DS80PCI102 senses its READEN pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE pin low. By connecting the DONE pin of each DS80PCI102 to the READEN pin of the next DS80PCI102, each DS80PCI102 can read its initial configuration from the EEPROM without causing bus contention.

DS80PCI102 30156916.gifFigure 9. Typical Multi-Device EEPROM Connection Diagram

7.5.6.2 EEPROM Address Mapping

A detailed EEPROM Address Mapping for a single device is shown in Table 7. For instances where multiple devices are written to EEPROM, the device starting address definitions align starting with Byte 0x03. A register map overview for a multi-device EEPROM address map is shown in Table 8.

7.6 Register Maps

Table 7. Single Device with Default Value

EEPROM Address Byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Description 0x00 CRC_EN Address Map Present EEPROM > 256 Bytes Reserved DEVICE COUNT[3] DEVICE COUNT[2] DEVICE COUNT[1] DEVICE COUNT[0]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x01 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x02 Max EEPROM Burst size[7] Max EEPROM Burst size[6] Max EEPROM Burst size[5] Max EEPROM Burst size[4] Max EEPROM Burst size[3] Max EEPROM Burst size[2] Max EEPROM Burst size[1] Max EEPROM Burst size[0]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x03 Reserved Reserved Reserved Reserved Reserved Reserved PWDN CH B PWDN CH A
SMBus Register 0x01[7] 0x01[6] 0x01[5] 0x01[4] 0x01[3] 0x01[2] 0x01[1] 0x01[0]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x04 Reserved Reserved PWDN_Inputs PWDN_Osc Override PRST Reserved Reserved Reserved
SMBus Register 0x02[5] 0x02[4] 0x02[3] 0x02[2] 0x02[0] 0x04[7] 0x04[6] 0x04[5]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x05 Reserved Reserved Reserved Reserved Reserved Reserved Ovrd IDLE_TH Reserved
SMBus Register 0x04[4] 0x04[3] 0x04[2] 0x04[1] 0x04[0] 0x06[4] 0x08[6] 0x08[5]
Default Value 0x04 0 0 0 0 0 1 0 0
Description 0x06 Reserved Ovrd RXDET Ovrd RATE Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x08[4] 0x08[3] 0x08[2] 0x08[1] 0x08[0] 0x0B[6] 0x0B[5] 0x0B[4]
Default Value 0x07 0 0 0 0 0 1 1 1
Description 0x07 Reserved Reserved Reserved Reserved Reserved Reserved RXDET_A_1 RXDET_A_0
SMBus Register 0x0B[3] 0x0B[2] 0x0B[1] 0x0B[0] 0x0E[5] 0x0E[4] 0x0E[3] 0x0E[2]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x08 CHA_EQ[7] CHA_EQ[6] CHA_EQ[5] CHA_EQ[4] CHA_EQ[3] CHA_EQ[2] CH0_EQ[1] CH0_EQ[0]
SMBus Register 0x0F[7] 0x0F[6] 0x0F[5] 0x0F[4] 0x0F[3] 0x0F[2] 0x0F[1] 0x0F[0]
Default Value 0x2F 0 0 1 0 1 1 1 1
Description 0x09 CHA_Sel SCP CHA_Sel RATE Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x10[7] 0x10[6] 0x10[5] 0x10[4] 0x10[3] 0x10[2] 0x10[1] 0x10[0]
Default Value 0xED 1 1 1 0 1 1 0 1
Description 0x0A CHA_DEM[2] CHA_DEM[1] CHA_DEM[0] Reserved CHA_Idle_ThA[1] CHA_Idle_ThA[0] CHA_Idle_ThD[1] CHA_Idle_ThD[0]
SMBus Register 0x11[2] 0x11[1] 0x11[0] 0x12[7] 0x12[3] 0x12[2] 0x12[1] 0x12[0]
Default Value 0x40 0 1 0 0 0 0 0 0
Description 0x0B Reserved Reserved RXDET_B_1 RXDET_B_0 CHB_EQ[7] CHB_EQ[6] CHB_EQ[5] CHB_EQ[4]
SMBus Register 0x15[5] 0x15[4] 0x15[3] 0x15[2] 0x16[7] 0x16[6] 0x16[5] 0x16[4]
Default Value 0x02 0 0 0 0 0 0 1 0
Description 0x0C CHB_EQ[3] CHB_EQ[2] CHB_EQ[1] CHB_EQ[0] CHB_Sel SCP CHB_Sel RATE Reserved Reserved
SMBus Register 0x16[3] 0x16[2] 0x16[1] 0x16[0] 0x17[7] 0x17[6] 0x17[5] 0x17[4]
Default Value 0xFE 1 1 1 1 1 1 1 0
Description 0x0D Reserved Reserved Reserved Reserved CHB_DEM[2] CHB_DEM[1] CHB_DEM[0] Reserved
SMBus Register 0x17[3] 0x17[2] 0x17[1] 0x17[0] 0x18[2] 0x18[1] 0x18[0] 0x19[7]
Default Value 0xD4 1 1 0 1 0 1 0 0
Description 0x0E CHB_Idle_ThA[1] CHB_Idle_ThA[0] CHB_Idle_ThD[1] CHB_Idle_ThD[0] Reserved Reserved Reserved Reserved
SMBus Register 0x19[3] 0x19[2] 0x19[1] 0x19[0] 0x1C[5] 0x1C[4] 0x1C[3] 0x1C[2]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x0F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x1D[7] 0x1D[6] 0x1D[5] 0x1D[4] 0x1D[3] 0x1D[2] 0x1D[1] 0x1D[0]
Default Value 0x2F 0 0 1 0 1 1 1 1
Description 0x10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x1E[7] 0x1E[6] 0x1E[5] 0x1E[4] 0x1E[3] 0x1E[2] 0x1E[1] 0x1E[0]
Default Value 0xAD 1 0 1 0 1 1 0 1
Description 0x11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x1F[2] 0x1F[1] 0x1F[0] 0x20[7] 0x20[3] 0x20[2] 0x20[1] 0x20[0]
Default Value 0x40 0 1 0 0 0 0 0 0
Description 0x12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x23[5] 0x23[4] 0x23[3] 0x23[2] 0x24[7] 0x24[6] 0x24[5] 0x24[4]
Default Value 0x02 0 0 0 0 0 0 1 0
Description 0x13 Reserved Reserved Reserved Reserved Reserved Reserved Reserved CHA_VOD[2]
SMBus Register 0x24[3] 0x24[2] 0x24[1] 0x24[0] 0x25[7] 0x25[6] 0x25[5] 0x25[4]
Default Value 0xFA 1 1 1 1 1 0 1 0
Description 0x14 CHA_VOD[1] CHA_VOD[0] Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x25[3] 0x25[2] 0x25[1] 0x25[0] 0x26[2] 0x26[1] 0x26[0] 0x27[7]
Default Value 0xD4 1 1 0 1 0 1 0 0
Description 0x15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x27[3] 0x27[2] 0x27[1] 0x27[0] 0x28[6] 0x28[5] 0x28[4] 0x28[3]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x28[2] 0x28[1] 0x28[0] 0x2B[5] 0x2B[4] 0x2B[3] 0x2B[2] 0x2C[7]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x17 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x2C[6] 0x2C[5] 0x2C[4] 0x2C[3] 0x2C[2] 0x2C[1] 0x2C[0] 0x2D[7]
Default Value 0x5F 0 1 0 1 1 1 1 1
Description 0x18 Reserved Reserved CHB_VOD[2] CHB_VOD[1] CHB_VOD[0] Reserved Reserved Reserved
SMBus Register 0x2D[6] 0x2D[5] 0x2D[4] 0x2D[3] 0x2D[2] 0x2D[1] 0x2D[0] 0x2E[2]
Default Value 0x5A 0 1 0 1 1 0 1 0
Description 0x19 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x2E[1] 0x2E[0] 0x2F[7] 0x2F[3] 0x2F[2] 0x2F[1] 0x2F[0] 0x32[5]
Default Value 0x80 1 0 0 0 0 0 0 0
Description 0x1A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x32[4] 0x32[3] 0x32[2] 0x33[7] 0x33[6] 0x33[5] 0x33[4] 0x33[3]
Default Value 0x05 0 0 0 0 0 1 0 1
Description 0x1B Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x33[2] 0x33[1] 0x33[0] 0x34[7] 0x34[6] 0x34[5] 0x34[4] 0x34[3]
Default Value 0xF5 1 1 1 1 0 1 0 1
Description 0x1C Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x34[2] 0x34[1] 0x34[0] 0x35[2] 0x35[1] 0x35[0] 0x36[7] 0x36[3]
Default Value 0xA8 1 0 1 0 1 0 0 0
Description 0x1D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x36[2] 0x36[1] 0x36[0] 0x39[5] 0x39[4] 0x39[3] 0x39[2] 0x3A[7]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x1E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x3A[6] 0x3A[5] 0x3A[4] 0x3A[3] 0x3A[2] 0x3A[1] 0x3A[0] 0x3B[7]
Default Value 0x5F 0 1 0 1 1 1 1 1
Description 0x1F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x3B[6] 0x3B[5] 0x3B[4] 0x3B[3] 0x3B[2] 0x3B[1] 0x3B[0] 0x3C[2]
Default Value 0x5A 0 1 0 1 1 0 1 0
Description 0x20 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x3C[1] 0x3C[0] 0x3D[7] 0x3D[3] 0x3D[2] 0x3D[1] 0x3D[0] 0x40[5]
Default Value 0x80 1 0 0 0 0 0 0 0
Description 0x21 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x40[4] 0x40[3] 0x40[2] 0x41[7] 0x41[6] 0x41[5] 0x41[4] 0x41[3]
Default Value 0x05 0 0 0 0 0 1 0 1
Description 0x22 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x41[2] 0x41[1] 0x41[0] 0x42[7] 0x42[6] 0x42[5] 0x42[4] 0x42[3]
Default Value 0xF5 1 1 1 1 0 1 0 1
Description 0x23 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x42[2] 0x42[1] 0x42[0] 0x43[2] 0x43[1] 0x43[0] 0x44[7] 0x44[3]
Default Value 0xA8 1 0 1 0 1 0 0 0
Description 0x24 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x44[2] 0x44[1] 0x44[0] 0x47[3] 0x47[2] 0x47[1] 0x47[0] 0x48[7]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x25 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x48[6] 0x4C[7] 0x4C[6] 0x4C[5] 0x4C[4] 0x4C[3] 0x4C[0] 0x59[0]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x26 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x5A[7] 0x5A[6] 0x5A[5] 0x5A[4] 0x5A[3] 0x5A[2] 0x5A[1] 0x5A[0]
Default Value 0x54 0 1 0 1 0 1 0 0
Description 0x27 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x5B[7] 0x5B[6] 0x5B[5] 0x5B[4] 0x5B[3] 0x5B[2] 0x5B[1] 0x5B[0]
Default Value 0x54 0 1 0 1 0 1 0 0

Table 8. Multi-Device EEPROM Register Map Overview(1)(2)(3)(4)

Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BIt 0
Header 0 CRC EN Address Map EEPROM > 256 Bytes Reserved COUNT[3] COUNT[2] COUNT[1] COUNT[0]
1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
2 EE Burst[7] EE Burst[6] EE Burst[5] EE Burst[4] EE Burst[3] EE Burst[2] EE Burst[1] EE Burst[0]
Device 0
Info
3 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]
4 EE AD0 [7] EE AD0 [6] EE AD0 [5] EE AD0 [4] EE AD0 [3] EE AD0 [2] EE AD0 [1] EE AD0 [0]
Device 1
Info
5 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]
6 EE AD1 [7] EE AD1 [6] EE AD1 [5] EE AD1 [4] EE AD1 [3] EE AD1 [2] EE AD1 [1] EE AD1 [0]
Device 2
Info
7 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]
8 EE AD2 [7] EE AD2 [6] EE AD2 [5] EE AD2 [4] EE AD2 [3] EE AD2 [2] EE AD2 [1] EE AD2 [0]
Device 3
Info
9 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]
10 EE AD3 [7] EE AD3 [6] EE AD3 [5] EE AD3 [4] EE AD3 [3] EE AD3 [2] EE AD3 [1] EE AD3 [0]
Device 0 Addr 3 11 Reserved Reserved Reserved Reserved Reserved Reserved PWDN CH B PWDN CH A
Device 0 Addr 4 12 Reserved Reserved PDWN Inp PDWN OSC Ovrd PRST Reserved Reserved Reserved
Device 0 Addr 38 46 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Device 0 Addr 39 47 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Device 1 Addr 3 48 Reserved Reserved Reserved Reserved Reserved Reserved PWDN CH B PWDN CH A
Device 1 Addr 4 49 Reserved Reserved PDWN Inp PDWN OSC Ovrd PRST Reserved Reserved Reserved
Device 1 Addr 38 83 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Device 1 Addr 39 84 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Device 2 Addr 3 85 Reserved Reserved Reserved Reserved Reserved Reserved PWDN CH B PWDN CH A
Device 2 Addr 4 86 Reserved Reserved PDWN Inp PDWN OSC Ovrd PRST Reserved Reserved Reserved
Device 2 Addr 38 120 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Device 2 Addr 39 121 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Device 3 Addr 3 122 Reserved Reserved Reserved Reserved Reserved Reserved PWDN CH B PWDN CH A
Device 3 Addr 4 123 Reserved Reserved PDWN Inp PDWN OSC Ovrd PRST Reserved Reserved Reserved
Device 3 Addr 38 157 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Device 3 Addr 39 158 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
(1) CRC EN = 1; Address Map = 1
(2) EEPROM > 256 Bytes = 0
(3) COUNT[3:0] = 0011'b
(4) Multiple DS80PCI102 devices may point at the same address space if they have identical programming values.

Table 9. Multi DS80PCI102 EEPROM Data

EEPROM Address Address (Hex) EEPROM Data Comments
0 00 0x43 CRC_EN = 0, Address Map = 1, Device Count = 3 (Devices 0, 1, 2, and 3)
1 01 0x00
2 02 0x08 EEPROM Burst Size
3 03 0x00 CRC not used
4 04 0x0B Device 0 Address Location
5 05 0x00 CRC not used
6 06 0x30 Device 1 Address Location
7 07 0x00 CRC not used
8 08 0x30 Device 2 Address Location
9 09 0x00 CRC not used
10 0A 0x0B Device 3 Address Location
11 0B 0x00 Begin Device 0 and Device 3 - Address Offset 3
12 0C 0x00
13 0D 0x04
14 0E 0x07
15 0F 0x00
16 10 0x2F Default EQ CHA
17 11 0xED
18 12 0x40
19 13 0x02 Default EQ CHB
20 14 0xFE Default EQ CHB
21 15 0xD4
22 16 0x00
23 17 0x2F
24 18 0xAD
25 19 0x40
26 1A 0x02
27 1B 0xFA PCI102 CHA VOD = 1000 mVpp
28 1C 0xD4 PCI102 CHA VOD = 1000 mVpp
29 1D 0x01
30 1E 0x80
31 1F 0x5F
32 20 0x56 PCI102 CHB VOD = 1000 mVpp
33 21 0x80
34 22 0x05
35 23 0xF5
36 24 0xA8
37 25 0x00
38 26 0x5F
39 27 0x5A
40 28 0x80
41 29 0x05
42 2A 0xF5
43 2B 0xA8
44 2C 0x00
45 2D 0x00
46 2E 0x54
47 2F 0x54 End Device 0 and Device 3 - Address Offset 39
48 30 0x00 Begin Device 1 and Device 2 - Address Offset 3
49 31 0x00
50 32 0x04
51 33 0x07
52 34 0x00
53 35 0x2F Default EQ CHA
54 36 0xED
55 37 0x40
56 38 0x02 Default EQ CHB
57 39 0xFE Default EQ CHB
58 3A 0xD4
59 3B 0x00
60 3C 0x2F
61 3D 0xAD
62 3E 0x40
63 3F 0x02
64 40 0xFA PCI102 CHA VOD = 1000 mVpp
65 41 0xD4 PCI102 CHA VOD = 1000 mVpp
66 42 0x01
67 43 0x80
68 44 0x5F
69 45 0x56 PCI102 CHB VOD = 1000 mVpp
70 46 0x80
71 47 0x05
72 48 0xF5
73 49 0xA8
74 4A 0x00
75 4B 0x5F
76 4C 0x5A
77 4D 0x80
78 4E 0x05
79 4F 0xF5
80 50 0xA8
81 51 0x00
82 52 0x00
83 53 0x54
84 54 0x54 End Device 1 and Device 2 - Address Offset 39

Table 10. SMBus Register Map

Address Register Name Bit Field Type Default EEPROM Bit Description
0x00 Device Address Observation 7 Reserved R/W 0x00 Reserved
SMBus strap observation
6:3 I2C Address [3:0] R
2 EEPROM reading done R 1: Device completed the read from external EEPROM
1 Reserved RWSC Reserved
0 Reserved RWSC Reserved
0x01 Control 1 7:2 Reserved R/W 0x00 Yes Reserved
1:0 PWDN A/B [1]: Powerdown Channel B (1); Normal Operation (0)
[0]: Powerdown Channel A (1); Normal Operation (0)
0x02 Control 2 7 Override RXDET R/W 0x00 1 = Override Automatic Rx Detect State Machine Reset
6 RXDET Value 1 = Set Rx Detect State Machine Reset
0 = Clear Rx Detect State Machine Reset
5:4 Reserved Yes Reserved
3 PWDN Inputs Yes Reserved
2 PWDN Oscillator Yes Reserved
1 Reserved Reserved
0 Override PRSNT Yes 1: Enables Reg 0x01[1:0]
0: Normal Operation
0x03 Reserved 7:0 Reserved R/W 0x00 Reserved
0x04 Reserved 7:0 Reserved R/W 0x00 Yes Reserved
0x05 Reserved 7:0 Reserved R/W 0x00 Reserved
0x06 Slave Register Control 7:5 Reserved R/W 0x10 Reserved
4 Reserved Yes Reserved
3 Register Enable 1 = Enables SMBus Slave Mode Register Control
Note: To change VOD, DEM, and EQ of the channels in slave mode, this bit must be set to 1.
2:0 Reserved Reserved
0x07 Digital Reset and Control 7 Reserved R/W 0x01 Reserved
6 Reset Regs Self clearing reset for registers.
Writing a [1] will return register settings to default values.
5 Reset SMBus Master Self clearing reset to SMBus master state machine
4:0 Reserved Reserved
0x08 Pin Override 7 Reserved R/W 0x00 Reserved
6 Override Idle Threshold Yes [1]: Override by Channel - see Reg 0x12 and 0x19
[0]: SD_TH pin control
5:4 Reserved Yes Set bits to 0
3 Override RXDET Yes [1]: Force RXDET by Channel - see Reg 0x0E and 0x15
[0]: Normal Operation
2 Override RATE Yes [1]: Override by Channel - see Reg 0x10 and 0x17
[0]: Normal Operation
1:0 Reserved Yes Reserved
0x09 Reserved 7:0 Reserved R/W 0x00 Reserved
0x0A Reserved 7:0 Reserved R 0x00 Reserved
0x0B Reserved 7 Reserved R/W 0x70 Reserved
6:0 Reserved R/W Yes Reserved
0x0C Reserved 7:0 Reserved R/W 0x00 Reserved
0x0D Reserved 7:0 Reserved R/W 0x00 Reserved
0x0E CH A
RXDET Control
7:6 Reserved R/W 0x00 Reserved
5:4 Reserved Yes Reserved
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω Note: override RXDET pin.
1:0 Reserved Reserved
0x0F CH A
EQ Control
7:0 BOOST [7:0] R/W 0x2F Yes EQ Control - total of 256 levels
See Table 2
0x10 CH A
RATE Control
7 Sel_scp R/W 0xED Yes 1 = Short Circuit Protection ON
0 = Short Circuit Protection OFF
6 Sel_RATE Yes 1 = Select GEN1/2 Mode
0 = Select GEN3 Mode
5:3 Reserved Yes Reserved
2:0 Reserved Yes Reserved
0x11 CH A
DEM Control
7 Reserved R 0x82 Reserved
6:5 Rate Information Signal Rate Detected
00 = GEN1 (2.5G)
01 = GEN2 (5.0G)
11 = GEN3 (8.0G)
4:3 Reserved R/W Reserved
2:0 DEM [2:0] Yes DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x12 CH A
Idle Threshold
7 Reserved R/W 0x00 Yes Reserved
6:4 Reserved Reserved
3:2 idle_thA[1:0] Yes Assert Thresholds
Use only if register 0x08 [6] = 1
00 = 180 mV (Default)
01 = 160 mV
10 = 210 mV
11= 190 mV
1:0 idle_thD[1:0] Yes Deassert Thresholds
Use only if register 0x08 [6] = 1
00 = 110 mV (Default)
01 = 100 mV
10 = 150 mV
11= 130 mV
0x13 Reserved 7:0 Reserved R/W 0x00 Reserved
0x14 Reserved 7:0 Reserved R/W 0x00 Reserved
0x15 CH B
RXDET Control
7:6 Reserved R/W 0x00 Reserved
5:4 Reserved Yes Reserved
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω Note: override RXDET pin.
1:0 Reserved Reserved
0x16 CH B
EQ Control
7:0 BOOST [7:0] R/W 0x2F Yes EQ Control - total of 256 levels
See Table 2
0x17 CH B
RATE Control
7 Sel_scp R/W 0xED Yes 1 = Short Circuit Protection ON
0 = Short Circuit Protection OFF
6 Sel_RATE Yes 1 = Select GEN1/2 Mode
0 = Select GEN3 Mode
5:3 Reserved Yes Reserved
2:0 Reserved Yes Reserved
0x18 CH B
DEM Control
7 Reserved R 0x02 Reserved
6:5 Rate Information Signal Rate Detected
00 = GEN1 (2.5G)
01 = GEN2 (5.0G)
11 = GEN3 (8.0G)
4:3 Reserved R/W Reserved
2:0 DEM [2:0] Yes DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x19 CH B
Idle Threshold
7 Reserved R/W 0x00 Yes Reserved
6:4 Reserved Reserved
3:2 idle_thA[1:0] Yes Assert Thresholds
Use only if register 0x08 [6] = 1
00 = 180 mV (Default)
01 = 160 mV
10 = 210 mV
11= 190 mV
1:0 idle_thD[1:0] Yes Deassert Thresholds
Use only if register 0x08 [6] = 1
00 = 110 mV (Default)
01 = 100 mV
10 = 150 mV
11= 130 mV
0x1A-0x1B Reserved 7:0 Reserved R/W 0x00 Reserved
0x1C Reserved 7:6 Reserved R/W 0x00 Reserved
5:2 Reserved Yes Reserved
1:0 Reserved Reserved
0x1D Reserved 7:0 Reserved R/W 0x2F Yes Reserved
0x1E Reserved 7:0 Reserved R/W 0xAD Yes Reserved
0x1F Reserved 7:3 Reserved R/W 0x02 Reserved
2:0 Reserved Yes Reserved
0x20 Reserved 7 Reserved R/W 0x00 Yes Reserved
6:4 Reserved Reserved
3:0 Reserved Yes Reserved
0x21-0x22 Reserved 7:0 Reserved R/W 0x00 Reserved
0x23 Reserved 7:6 Reserved R/W 0x00 Reserved
5:2 Reserved Yes Reserved
1:0 Reserved Reserved
0x24 Reserved 7:0 Reserved R/W 0x2F Yes Reserved
0x25 CH A VOD 7:5 Reserved R/W 0xAD Yes Reserved
4:2 VOD CHA Control Yes VOD Control CHA
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V (default)
100: 1.1 V
101: 1.2 V
110: 1.3 V
111: 1.4 V
1:0 Reserved Yes Reserved
0x26 Reserved 7:3 Reserved R/W 0x02 Reserved
2:0 Reserved Yes Reserved
0x27 Reserved 7 Reserved R/W 0x00 Yes Reserved
6:4 Reserved Reserved
3:0 Reserved Yes Reserved
0x28 Idle Control 7 Reserved R/W 0x00 Reserved
6:0 Reserved Yes Reserved
0x29-0x2A Reserved 7:0 Reserved R/W 0x00 Reserved
0x2B Reserved 7:6 Reserved R/W 0x00 Reserved
5:2 Reserved Yes Reserved
1:0 Reserved Reserved
0x2C Reserved 7:0 Reserved R/W 0x2F Yes Reserved
0x2D CH B VOD 7:5 Reserved R/W 0xAD Yes Reserved
4:2 VOD CHB Control Yes VOD Control CHB
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V (default)
100: 1.1 V
101: 1.2 V
110: 1.3 V
111: 1.4 V
1:0 Reserved Yes Reserved
0x2E Reserved 7:3 Reserved R/W 0x02 Reserved
2:0 Reserved Yes Reserved
0x2F Reserved 7 Reserved R/W 0x00 Yes Reserved
6:4 Reserved Reserved
3:0 Reserved Yes Reserved
0x30-0x31 Reserved 7:0 Reserved R/W 0x00 Reserved
0x32 Reserved 7:6 Reserved R/W 0x00 Reserved
5:2 Reserved Yes Reserved
1:0 Reserved Reserved
0x33 Reserved 7:0 Reserved R/W 0x2F Yes Reserved
0x34 Reserved 7:0 Reserved R/W 0xAD Yes Reserved
0x35 Reserved 7:3 Reserved R/W 0x02 Reserved
2:0 Reserved Yes Reserved
0x36 Reserved 7 Reserved R/W 0x00 Yes Reserved
6:4 Reserved Reserved
3:0 Reserved Yes Reserved
0x37-0x38 Reserved 7:0 Reserved R/W 0x00 Reserved
0x39 Reserved 7:6 Reserved R/W 0x00 Reserved
5:2 Reserved Yes Reserved
1:0 Reserved Reserved
0x3A Reserved 7:0 Reserved R/W 0x2F Yes Reserved
0x3B Reserved 7:0 Reserved R/W 0xAD Yes Reserved
0x3C Reserved 7:3 Reserved R/W 0x02 Reserved
2:0 Reserved Yes Reserved
0x3D Reserved 7 Reserved R/W 0x00 Yes Reserved
6:4 Reserved Reserved
3:0 Reserved Yes Reserved
0x3E-0x3F Reserved 7:0 Reserved R/W 0x00 Reserved
0x40 Reserved 7:6 Reserved R/W 0x00 Reserved
5:2 Reserved Yes Reserved
1:0 Reserved Reserved
0x41 Reserved 7:0 Reserved R/W 0x2F Yes Reserved
0x42 Reserved 7:0 Reserved R/W 0xAD Yes Reserved
0x43 Reserved 7:3 Reserved R/W 0x02 Reserved
2:0 Reserved Yes Reserved
0x44 Reserved 7 Reserved R/W 0x00 Yes Reserved
6:4 Reserved Reserved
3:0 Reserved Yes Reserved
0x45 Reserved 7:0 Reserved R/W 0x00 Reserved
0x46 Reserved 7:0 Reserved R/W 0x38 Reserved
0x47 Reserved 7:4 Reserved R/W 0x00 Reserved
3:0 Reserved Yes Reserved
0x48 Reserved 7:6 Reserved R/W 0x05 Yes Reserved
5:0 Reserved Reserved
0x49-0x4B Reserved 7:0 Reserved R/W 0x00 Reserved
0x4C Reserved 7:3 Reserved R/W 0x00 Yes Reserved
2:1 Reserved Reserved
0 Reserved Yes Reserved
0x4D-0x50 Reserved 7:0 Reserved R/W 0x00 Reserved
0x51 Device Information 7:5 Version[2:0] R 0x77 011'b
4:0 Device ID[4:0] 1 0111'b
0x52 Reserved 7:0 Reserved R/W 0x00 Reserved
0x53 Reserved 7:0 Reserved R/W 0x00 Reserved
0x54 Reserved 7:0 Reserved R/W 0x00 Reserved
0x55 Reserved 7:0 Reserved R/W 0x00 Reserved
0x56 Reserved 7:0 Reserved R/W 0x10 Reserved
0x57 Reserved 7:0 Reserved R/W 0x64 Reserved
0x58 Reserved 7:0 Reserved R/W 0x21 Reserved
0x59 Reserved 7:1 Reserved R/W 0x00 Reserved
0 Reserved Yes Reserved
0x5A Reserved 7:0 Reserved R/W 0x54 Yes Reserved
0x5B Reserved 7:0 Reserved R/W 0x54 Yes Reserved
0x5C Reserved 7:0 Reserved R/W 0x00 Reserved
0x5D Reserved 7:0 Reserved R/W 0x00 Reserved
0x5E Reserved 7:0 Reserved R/W 0x00 Reserved
0x5F Reserved 7:0 Reserved R/W 0x00 Reserved
0x60 Reserved 7:0 Reserved R/W 0x00 Reserved
0x61 Reserved 7:0 Reserved R/W 0x00 Reserved