SNLS401C February   2012  – September 2018 DS90C187

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Typical Application
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     DS90C187 Pin Descriptions — Serializer
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Input Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 AC Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Device Functional Modes
      1. 8.3.1  Device Configuration
      2. 8.3.2  Single Pixel Input / Single Pixel Output
      3. 8.3.3  Single Pixel Input / Dual Pixel Output
      4. 8.3.4  Dual Pixel Input / Dual Pixel Output
      5. 8.3.5  Pixel Clock Edge Select (RFB)
      6. 8.3.6  Power Management
      7. 8.3.7  Sleep Mode (PDB)
      8. 8.3.8  LVDS Outputs
      9. 8.3.9  18 bit / 24 bit Color Mode (18B)
      10. 8.3.10 LVCMOS Inputs
    4. 8.4 Programming
      1. 8.4.1 LVDS Interface / TFT Color Data Recommended Mapping
        1. 8.4.1.1 Color Mapping Information
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LVDS Interconnect Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Sequence
    2. 10.2 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 Single Pixel Input / Dual Pixel Output

When MODE0 is HIGH and MODE1 is LOW, data from INA_[27:0], HS, VS and DE is serialized and driven out on OA_[3:0]+/- and OB_[3:0]+/- with OA_C+/- and OB_C+/-. If 18B_MODE is LOW, then OA_3+/- and OB_3+/- are powered down and the corresponding LVCMOS input signals are ignored. The input LVCMOS data is split into odd and even pixels starting with the odd (first) pixel outputs OA_[3:0]+/- and then the even (second) pixel outputs OB_[3:0]+/-. The splitting of the data signals starts with DE (data enable) transitioning from logic LOW to HIGH indicating active data (see Figure 10). The number of clock cycles during blanking must be an EVEN number. This configuration will allow the user to interface with two FPD-Link receivers or other dual pixel inputs.

In this configuration IN_CLK can range from 50 MHz to 185 MHz, resulting in a total maximum payload of 1.4 Gbps (28 bits * 50 MHz) to 5.18 Gbps (28 bits * 185 MHz). Each LVDS driver will operate at a speed of 7 bits per 2 input clock cycles, resulting in a serial line rate of 175 Mbps to 647.5 Mbps. OA_C+/- and OA_B+/- will operate at ½ the rate as IN_CLK with a duty cycle ratio of 57:43.

  1. Disable the clock and data.
  2. Toggle PDB to Low and then High.
  3. After PDB settles reset the data pattern and enable the clock and data.