SNLS316G September   2009  – December 2015 DS90UR907Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  Recommended Timing for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  DC and AC Serial Control Bus Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Data Transfer
      2. 7.3.2 Operating Modes And Backward Compatibility - Config[1:0]
      3. 7.3.3 Video Control Signal Filter
      4. 7.3.4 Color Bit Mapping Select
      5. 7.3.5 EMI Reduction Features
        1. 7.3.5.1 Spread Spectrum Compatibility
      6. 7.3.6 Signal Quality Enhancers
        1. 7.3.6.1 VOD Select (VODSEL)
        2. 7.3.6.2 De-Emphasis (De-Emph)
      7. 7.3.7 Power Saving Features
        1. 7.3.7.1 Power-Down Feature (PDB)
        2. 7.3.7.2 Stop Clock Feature
        3. 7.3.7.3 1.8-V or 3.3-V VDDIO Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes and Backward Compatibility (Config[1:0])
    5. 7.5 Programming
      1. 7.5.1 Optional Serial Bus Control
      2. 7.5.2 Built In Self Test (BIST)
      3. 7.5.3 Optional Serial Bus Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-Up Requirements and PDB Pin
      2. 8.1.2 Transmission Media
      3. 8.1.3 Alternate Color / Data Mapping
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout and Power System Considerations
      2. 10.1.2 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • NJK|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(9)
MIN MAX UNIT
Supply voltage – VDDn (1.8 V) –0.3 2.5 V
Supply voltage – VDDIO −0.3 4 V
LVCMOS I/O voltage −0.3 VDDIO + 0.3 V
LVDS input voltage −0.3 VDDIO + 0.3 V
Driver output voltage −0.3 VDDn + 0.3 V
Junction temperature 150 °C
Storage temperature −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings—JEDEC

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±8000 V
Charged-device model (CDM), per AEC Q100-011 ±1250
Machine model ±250
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings—IEC and ISO

VALUE UNIT
V(ESD) Electrostatic discharge RD = 330 Ω, CS = 150 pF IEC, powered-up only contact discharge (RIN+, RIN−) ≥±6000 V
IEC, powered-up only air-gap discharge (RIN+, RIN−) ≥±30000
RD = 330 Ω, CS = 150 and 330 pF ISO10605 contact discharge (RIN+, RIN−) ≥±8000 V
ISO10605 air-gap discharge (RIN+, RIN−) ≥±15000
RD = 2 kΩ, CS = 150 and 330 pF ISO10605 contact discharge (RIN+, RIN−) ≥±8000 V
ISO10605 air-gap discharge (RIN+, RIN−) ≥±15000

6.4 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply Voltage (VDDn) 1.71 1.8 1.89 V
LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V
OR
LVCMOS Supply Voltage (VDDIO) 3 3.3 3.6 V
Operating Free Air Temperature (TA) −40 25 105 °C
RxCLKIN Frequency 5 65 MHz
Supply Noise(6) 100 mVP-P

6.5 Thermal Information

THERMAL METRIC(1) DS90UR907Q-Q1 UNIT
NJK (WQFN)
36 PINS
RθJA Junction-to-ambient thermal resistance 33.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.8 °C/W
RθJB Junction-to-board thermal resistance 7.2 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 7.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
LVCMOS INPUT DC SPECIFICATIONS
VIH High Level Input Voltage VDDIO = 3 to 3.6 V PDB, VODSEL,
MAPSEL,
CONFIG[1:0],BISTEN		 2.2 VDDIO V
VDDIO = 1.71 to 1.89 V 0.65* VDDIO VDDIO
VIL Low Level Input Voltage VDDIO = 3 to 3.6 V GND 0.8 V
VDDIO = 1.71 to 1.89 V GND 0.35* VDDIO
IIN Input Current VIN = 0 V or VDDIO VDDIO = 3
to 3.6 V		 –15 ±1 15 μA
VDDIO = 1.7
to 1.89 V		 –15 ±1 15
FPD-LINK LVDS RECEIVER DC SPECIFICATIONS
VTH Differential Threshold High Voltage VCM = 1.2 V, Figure 1 RxIN[3:0]+/-, RxCLKIN+/-, 100 mV
VTL Differential Threshold Low Voltage –100
|VID| Differential Input Voltage Swing 200 600 mV
VCM Common Mode Voltage VDDIO = 3.3 V 0 1.2 2.4 V
VDDIO = 1.8 V 0 1.2 1.55
IIN Input Current −15 ±1 15 μA
FPD-LINK II LVDS DRIVER DC SPECIFICATIONS
VOD Differential Output Voltage RL = 100 Ω,
De-Emph = disabled, Figure 3		 VODSEL = 0 DOUT+, DOUT- ±225 ±300 ±375 mV
VODSEL = 1 ±350 ±450 ±550
VODp-p Differential Output Voltage
(DOUT+) – (DOUT-)		 VODSEL = 0 600 mVp-p
VODSEL = 1 900 mVp-p
ΔVOD Output Voltage Unbalance RL = 100 Ω, De-Emph = disabled, VODSEL = L 1 50 mV
VOS Offset Voltage – Single-ended
At TP A and B, Figure 2		 RL = 100 Ω,
De-Emph = disabled		 VODSEL = 0 1.65 V
VODSEL = 1 1.575 V
ΔVOS Offset Voltage Unbalance
Single-ended
At TP A and B, Figure 2		 RL = 100 Ω, De-Emph = disabled 1 mV
IOS Output Short-Circuit Current DOUT± = 0 V,
De-Emph = disabled		 VODSEL = 0 –35 mA
RT Internal Termination Resistor 80 120 Ω
SUPPLY CURRENT
IDDT1 Supply Current
(includes load current)
RL = 100 Ω, f = 65 MHz		 Checker Board Pattern,
De-Emph = 3 kΩ,
VODSEL = H, Figure 10		 VDD= 1.89 V All VDD pins 80 90 mA
IDDIOT1 VDDIO= 1.89 V VDDIO 3 5 mA
VDDIO = 3.6 V 10 13 mA
IDDT2 Checker Board Pattern,
De-Emph = 6 kΩ,
VODSEL = L, Figure 10		 VDD= 1.89 V All VDD pins 75 85 mA
IDDIOT2 VDDIO= 1.89 V VDDIO 3 5 mA
VDDIO = 3.6 V 10 13 mA
IDDZ Supply Current Power Down PDB = 0 V , (All other LVCMOS Inputs = 0 V) VDD= 1.89 V All VDD pins 60 1000 µA
IDDIOZ VDDIO= 1.89 V VDDIO 0.5 10 µA
VDDIO = 3.6 V 1 30 µA

6.7 Recommended Timing for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN NOM MAX Units
fSCL SCL Clock Frequency Standard Mode 0 100 kHz
Fast Mode 0 400
tLOW SCL Low Period Standard Mode 4.7 us
Fast Mode 1.3
tHIGH SCL High Period Standard Mode 4 us
Fast Mode 0.6
tHD;STA Hold time for a start or a repeated start condition,
Figure 12		 Standard Mode 4 us
Fast Mode 0.6
tSU:STA Set Up time for a start or a repeated start condition,
Figure 12		 Standard Mode 4.7 us
Fast Mode 0.6
tHD;DAT Data Hold Time,
Figure 12		 Standard Mode 0 3.45 us
Fast Mode 0 0.9
tSU;DAT Data Set Up Time,
Figure 12		 Standard Mode 250 ns
Fast Mode 100
tSU;STO Set Up Time for STOP Condition, Figure 12 Standard Mode 4 us
Fast Mode 0.6
tBUF Bus Free Time
Between STOP and START,
Figure 12		 Standard Mode 4.7 us
Fast Mode 1.3
tr SCL and SDA Rise Time,
Figure 12		 Standard Mode 1000 ns
Fast Mode 300
tf SCL and SDA Fall Time,
Figure 12		 Standard Mode 300 ns
Fast mode 300

6.8 Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FPD-LINK LVDS INPUT
tRSP0 Receiver Strobe Position-bit 0 RxCLKIN = 65 MHz,
RxIN[3:0]
Figure 5		 0.66 1.1 1.54 ns
tRSP1 Receiver Strobe Position-bit 1 2.86 3.3 3.74 ns
tRSP2 Receiver Strobe Position-bit 2 5.05 5.5 5.93 ns
tRSP3 Receiver Strobe Position-bit 3 7.25 7.7 8.13 ns
tRSP4 Receiver Strobe Position-bit 4 9.45 9.90 10.33 ns
tRSP5 Receiver Strobe Position-bit 5 11.65 12.1 12.53 ns
tRSP6 Receiver Strobe Position-bit 6 13.85 14.30 14.73 ns
FPD-LINK II LVDS OUTPUT
tHLT Output Low-to-High Transition Time, Figure 4 RL = 100 Ω, De-Emphasis = disabled, VODSEL = 0 200 ps
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 1 200
tHLT Output High-to-Low Transition Time, Figure 4 RL = 100 Ω, De-Emphasis = disabled, VODSEL = 0 200 ps
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 1 200
tXZD Ouput Active to OFF Delay, Figure 7 5 15 ns
tPLD PLL Lock Time, Figure 6 RL = 100 Ω(4) 1.5 10 ms
tSD Delay - Latency, Figure 8 RL = 100 Ω 140*T 145*T ns
tDJIT Output Total Jitter,
Figure 9		 RL = 100 Ω, De-Emphasis = disabled,
RANDOM pattern, RxCLKIN = 43 and 65 MHz(5)		 0.26 UI
λSTXBW Jitter Transfer
Function –3-dB Bandwidth(7) (8)		 RxCLKIN = 43 MHz 2.2 MHz
RxCLKIN = 65 MHz 3
δSTX Jitter Transfer
Function Peaking(7)(8)		 RxCLKIN = 43 MHz 1 dB
RxCLKIN = 65 MHz 1

6.9 DC and AC Serial Control Bus Characteristics

Over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Level SDA and SCL 0.7*
VDDIO		 VDDIO V
VIL Input Low Level Voltage SDA and SCL GND 0.3*
VDDIO		 V
VHY Input Hysteresis >50 mV
VOL SDA, IOL = 1.25 mA 0 0.36 V
Iin SDA or SCL, Vin = VDDIO or GND –10 10 µA
tR SDA RiseTime – READ SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 12 430 ns
tF SDA Fall Time – READ 20 ns
tSU;DAT Set Up Time — READ See Figure 12 560 ns
tHD;DAT Hold Up Time — READ See Figure 12 615 ns
tSP Input Filter 50 ns
Cin Input Capacitance SDA or SCL <5 pF
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, Ta = 25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages.
(4) tPLD is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN.
(5) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*RxCLKIN). The UI scales with RxCLKIN frequency.
(6) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8 V) supply with amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the noise frequency is less than 400 kHz.
(7) Specification is ensured by characterization and is not tested in production.
(8) Specification is ensured by design and is not tested in production.
(9) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
DS90UR907Q-Q1 30105062.gif Figure 1. FPD-Link DC VTH/VTL Definition
DS90UR907Q-Q1 30105046.gif Figure 2. Output Test Circuit
DS90UR907Q-Q1 30105030.gif Figure 3. Output Waveforms
DS90UR907Q-Q1 30105047.gif Figure 4. Output Transition Times
DS90UR907Q-Q1 30105061.png Figure 5. RSP (Receiver Strobe Position)
DS90UR907Q-Q1 30105048.gif Figure 6. Lock Time
DS90UR907Q-Q1 30105049.gif Figure 7. Disable Time
DS90UR907Q-Q1 30105010.gif Figure 8. Latency Delay
DS90UR907Q-Q1 30105050.gif Figure 9. Output Jitter
DS90UR907Q-Q1 30105032.gif Figure 10. Checkerboard Data Pattern
DS90UR907Q-Q1 30105052.gif Figure 11. BIST Pass Waveform
DS90UR907Q-Q1 30105036.gif Figure 12. Serial Control Bus Timing Diagram

6.10 Typical Characteristics

DS90UR907Q-Q1 30105001.gif Figure 13. Typical IDDT (1.8-V Supply) Current as a Function of RxCLK