SPRS742J June   2011  – December 2017 F28M35E20B , F28M35H22C , F28M35H52C , F28M35M22C , F28M35M52C

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings - Automotive
    3. 5.3  ESD Ratings - Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics for RFP PowerPAD Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Power Sequencing
        1. 5.9.1.1 Power Management and Supervisory Circuit Solutions
      2. 5.9.2 Clock Specifications
        1. 5.9.2.1 Changing the Frequency of the Main PLL
        2. 5.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
        3. 5.9.2.3 Output Clock Frequency and Switching Characteristics
        4. 5.9.2.4 Internal Clock Frequencies
      3. 5.9.3 Timing Parameter Symbology
        1. 5.9.3.1 General Notes on Timing Parameters
        2. 5.9.3.2 Test Load Circuit
      4. 5.9.4 Flash Timing - Master Subsystem
      5. 5.9.5 Flash Timing - Control Subsystem
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
        2. 5.9.6.2 GPIO - Input Timing
        3. 5.9.6.3 Sampling Window Width for Input Signals
        4. 5.9.6.4 Low-Power Mode Wakeup Timing
      7. 5.9.7 External Interrupt Electrical Data and Timing
    10. 5.10 Analog and Shared Peripherals
      1. 5.10.1 Analog-to-Digital Converter
        1. 5.10.1.1 Sample Mode
        2. 5.10.1.2 Start-of-Conversion Triggers
        3. 5.10.1.3 Analog Inputs
        4. 5.10.1.4 ADC Result Registers and EOC Interrupts
        5. 5.10.1.5 ADC Electrical Data and Timing
      2. 5.10.2 Comparator + DAC Units
        1. 5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
      3. 5.10.3 Interprocessor Communications
      4. 5.10.4 External Peripheral Interface
        1. 5.10.4.1 EPI General-Purpose Mode
        2. 5.10.4.2 EPI SDRAM Mode
        3. 5.10.4.3 EPI Host Bus Mode
          1. 5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 5.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 5.10.4.3.1.3 HB-8 FIFO Mode
          2. 5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 5.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 5.10.4.3.2.3 HB-16 FIFO Mode
        4. 5.10.4.4 EPI Electrical Data and Timing
    11. 5.11 Master Subsystem Peripherals
      1. 5.11.1 Synchronous Serial Interface
        1. 5.11.1.1 Bit Rate Generation
        2. 5.11.1.2 Transmit FIFO
        3. 5.11.1.3 Receive FIFO
        4. 5.11.1.4 Interrupts
        5. 5.11.1.5 Frame Formats
      2. 5.11.2 Universal Asynchronous Receiver/Transmitter
        1. 5.11.2.1 Baud-Rate Generation
        2. 5.11.2.2 Transmit and Receive Logic
        3. 5.11.2.3 Data Transmission and Reception
        4. 5.11.2.4 Interrupts
      3. 5.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 5.11.3.1 Functional Overview
        2. 5.11.3.2 Available Speed Modes
        3. 5.11.3.3 I2C Electrical Data and Timing
      4. 5.11.4 Cortex-M3 Controller Area Network
        1. 5.11.4.1 Functional Overview
      5. 5.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 5.11.5.1 Functional Description
      6. 5.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 5.11.6.1 Functional Overview
        2. 5.11.6.2 MII Signals
        3. 5.11.6.3 EMAC Electrical Data and Timing
        4. 5.11.6.4 MDIO Electrical Data and Timing
    12. 5.12 Control Subsystem Peripherals
      1. 5.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 5.12.1.1 HRPWM Electrical Data and Timing
        2. 5.12.1.2 ePWM Electrical Data and Timing
          1. 5.12.1.2.1 Trip-Zone Input Timing
      2. 5.12.2 Enhanced Capture Module
        1. 5.12.2.1 eCAP Electrical Data and Timing
      3. 5.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 5.12.3.1 eQEP Electrical Data and Timing
      4. 5.12.4 C28x Inter-Integrated Circuit Module
        1. 5.12.4.1 Functional Overview
        2. 5.12.4.2 Clock Generation
        3. 5.12.4.3 I2C Electrical Data and Timing
      5. 5.12.5 C28x Serial Communications Interface
        1. 5.12.5.1 Architecture
        2. 5.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 5.12.6 C28x Serial Peripheral Interface
        1. 5.12.6.1 Functional Overview
        2. 5.12.6.2 SPI Electrical Data and Timing
          1. 5.12.6.2.1 Master Mode Timing
          2. 5.12.6.2.2 Slave Mode Timing
      7. 5.12.7 C28x Multichannel Buffered Serial Port
        1. 5.12.7.1 McBSP Electrical Data and Timing
          1. 5.12.7.1.1 McBSP Transmit and Receive Timing
          2. 5.12.7.1.2 McBSP as SPI Master or Slave Timing
  6. 6Detailed Description
    1. 6.1  Memory Maps
      1. 6.1.1 Control Subsystem Memory Map
      2. 6.1.2 Master Subsystem Memory Map
    2. 6.2  Identification
    3. 6.3  Master Subsystem
      1. 6.3.1 Cortex-M3 CPU
      2. 6.3.2 Cortex-M3 DMA and NVIC
      3. 6.3.3 Cortex-M3 Interrupts
      4. 6.3.4 Cortex-M3 Vector Table
      5. 6.3.5 Cortex-M3 Local Peripherals
      6. 6.3.6 Cortex-M3 Local Memory
      7. 6.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 6.4  Control Subsystem
      1. 6.4.1 C28x CPU/FPU/VCU
      2. 6.4.2 C28x Core Hardware Built-In Self-Test
      3. 6.4.3 C28x Peripheral Interrupt Expansion
      4. 6.4.4 C28x Direct Memory Access
      5. 6.4.5 C28x Local Peripherals
      6. 6.4.6 C28x Local Memory
      7. 6.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 6.5  Analog Subsystem
      1. 6.5.1 ADC1
      2. 6.5.2 ADC2
      3. 6.5.3 Analog Comparator + DAC
      4. 6.5.4 Analog Common Interface Bus
    6. 6.6  Master Subsystem NMIs
    7. 6.7  Control Subsystem NMIs
    8. 6.8  Resets
      1. 6.8.1 Cortex-M3 Resets
      2. 6.8.2 C28x Resets
      3. 6.8.3 Analog Subsystem and Shared Resources Resets
      4. 6.8.4 Device Boot Sequence
    9. 6.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 6.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 6.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 6.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 6.9.4 Connecting ARS and XRS Pins
    10. 6.10 Input Clocks and PLLs
      1. 6.10.1 Internal Oscillator (Zero-Pin)
      2. 6.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 6.10.3 External Oscillators (Pins X1 and XCLKIN)
      4. 6.10.4 Main PLL
      5. 6.10.5 USB PLL
    11. 6.11 Master Subsystem Clocking
      1. 6.11.1 Cortex-M3 Run Mode
      2. 6.11.2 Cortex-M3 Sleep Mode
      3. 6.11.3 Cortex-M3 Deep Sleep Mode
    12. 6.12 Control Subsystem Clocking
      1. 6.12.1 C28x Normal Mode
      2. 6.12.2 C28x IDLE Mode
      3. 6.12.3 C28x STANDBY Mode
    13. 6.13 Analog Subsystem Clocking
    14. 6.14 Shared Resources Clocking
    15. 6.15 Loss of Input Clock (NMI Watchdog Function)
    16. 6.16 GPIOs and Other Pins
      1. 6.16.1 GPIO_MUX1
      2. 6.16.2 GPIO_MUX2
      3. 6.16.3 AIO_MUX1
      4. 6.16.4 AIO_MUX2
    17. 6.17 Emulation/JTAG
    18. 6.18 Code Security Module
      1. 6.18.1 Functional Description
    19. 6.19 µCRC Module
      1. 6.19.1 Functional Description
      2. 6.19.2 CRC Polynomials
      3. 6.19.3 CRC Calculation Procedure
      4. 6.19.4 CRC Calculation for Data Stored In Secure Memory
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
      1. 8.3 Related Links
      2. 8.4 Community Resources
      3. 8.5 Trademarks
      4. 8.6 Electrostatic Discharge Caution
      5. 8.7 Glossary
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information
  10. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview

Features

  • Master Subsystem — ARM® Cortex®-M3
    • Up to 100 MHz
    • Embedded Memory
      • Up to 512KB of Flash (ECC)
      • Up to 32KB of RAM (ECC or Parity)
      • Up to 64KB of Shared RAM
      • 2KB of IPC Message RAM
    • Five Universal Asynchronous Receiver/Transmitters (UARTs)
    • Four Synchronous Serial Interfaces (SSIs) and a Serial Peripheral Interface (SPI)
    • Two Inter-integrated Circuits (I2Cs)
    • Universal Serial Bus On-the-Go (USB-OTG) + PHY
    • 10/100 ENET 1588 MII
    • Two Controller Area Network, D_CAN, Modules (Pin-Bootable)
    • 32-Channel Micro Direct Memory Access (µDMA)
    • Dual Security Zones (128-Bit Password per Zone)
    • External Peripheral Interface (EPI)
    • Micro Cyclic Redundancy Check (µCRC) Module
    • Four General-Purpose Timers
    • Two Watchdog Timer Modules
    • Endianness: Little Endian
  • Clocking
    • On-chip Crystal Oscillator and External Clock Input
    • Dynamic Phase-Locked Loop (PLL) Ratio Changes Supported
  • 1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design
  • Interprocessor Communications (IPC)
    • 32 Handshaking Channels
    • Four Channels Generate IPC Interrupts
    • Can be Used to Coordinate Transfer of Data Through IPC Message RAMs
  • Up to 74 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins
    • Glitch-free I/Os
  • Control Subsystem — TMS320C28x 32-Bit CPU
    • Up to 150 MHz
    • C28x Core Hardware Built-in Self-Test
    • Embedded Memory
      • Up to 512KB of Flash (ECC)
      • Up to 36KB of RAM (ECC or Parity)
      • Up to 64KB of Shared RAM
      • 2KB of IPC Message RAM
    • IEEE-754 Single-Precision Floating-Point Unit (FPU)
    • Viterbi, Complex Math, CRC Unit (VCU)
    • Serial Communications Interface (SCI)
    • SPI
    • I2C
    • 6-Channel Direct Memory Access (DMA)
    • Nine Enhanced Pulse Width Modulator (ePWM) Modules
      • 18 Outputs (16 High-Resolution)
    • Six 32-Bit Enhanced Capture (eCAP) Modules
    • Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Multichannel Buffered Serial Port (McBSP)
    • EPI
    • One Security Zone (128-Bit Password)
    • Three 32-Bit Timers
    • Endianness: Little Endian
  • Analog Subsystem
    • Dual 12-Bit Analog-to-Digital Converters (ADCs)
    • Up to 2.88 MSPS
    • Up to 20 Channels
    • Four Sample-and-Hold (S/H) Circuits
    • Up to Six Comparators With 10-Bit Digital-to-Analog Converter (DAC)
  • Package
    • 144-Pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP)
  • Temperature Options:
    • T: –40ºC to 105ºC Junction
    • S: –40ºC to 125ºC Junction
    • Q: –40ºC to 125ºC Free-Air
      (AEC Q100 Qualification for Automotive Applications)

Description

The Concerto family is a multicore system-on-chip microcontroller unit (MCU) with independent communication and real-time control subsystems. The F28M35x family of devices is the first series in the Concerto family.

The communications subsystem is based on the industry-standard 32-bit ARM Cortex-M3 CPU and features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, Controller Area Network (CAN), UART, SSI, I2C, and an external interface.

The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x floating-point CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault protection, and encoders and captures—all as implemented by TI’s TMS320C2000™ Piccolo™ and Delfino™ families. In addition, the C28-CPU has been enhanced with the addition of the VCU instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms.

A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code (ECC), parity, and code secure memory, as well as documentation to assist with system-level industrial safety certification.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
F28M35H52CRFP HTQFP (144) 20.0 mm × 20.0 mm
F28M35H22CRFP HTQFP (144) 20.0 mm × 20.0 mm
F28M35M52CRFP HTQFP (144) 20.0 mm × 20.0 mm
F28M35M20BRFP HTQFP (144) 20.0 mm × 20.0 mm
F28M35E20BRFP HTQFP (144) 20.0 mm × 20.0 mm
For more information on these devices, see Mechanical, Packaging, and Orderable Information.

Functional Block Diagram

F28M35H52C F28M35H22C F28M35M52C F28M35M22C F28M35M20B F28M35E20B fbd_prs742.gif
Some peripherals are not available on the F28M35Mx and F28M35Ex devices.
Figure 1-1 Functional Block Diagram