SLAS975A November   2013  – August 2015 HD3SS6126

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Device Parameters
    6. 6.6 Electrical Characteristics - Signal Switch Parameters
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Supply
        2. 8.2.2.2 Differential Pairs
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The HD3SS6126 is a USB 3.0 and USB 2.0 differential switch, it is designed to support data rates up to 10 Gbps on high-bandwidth paths (SS), it is also suitable for DisplayPort, PCIe Gen1/2/3, SATA 1.5/3/6G, SAS 1.5/3/6G and XAUI applications. The device uses a unique adaptation method to maintain a constant channel impedance over the supported common-mode voltage range, resulting in an excellent high-bandwidth path dynamic characteristics (at 2.5 GHz; Crosstalk = –35 dB, Isolation = –23 dB, Insertion Loss = –1.1 dB, Return Loss = –11 dB).

7.2 Functional Block Diagram

HD3SS6126 fun_diagram_SLAS975.gif

7.3 Feature Description

The HD3SS6126 can be powered by VBUS from the USB Host, and is capable of selecting USB2 independently from USB3. Although the main application of the HD3SS6126 is USB3.0/2.0, the device also supports common interfaces such as PCIe Gen1 and Gen2, DP and SATA/SAS applications. The device is able to support these additional interfaces because of its support of data rates up to 5.4 Gbps and common-mode voltages from 0 V to 2 V with a maximum signal swing of 1.8 V. All of these applications use an 8b or 10b coding technique to achieve DC balance and facilitate terminal equipment.

NOTE

The device may need AC capacitors and additional bias voltage to support the PCIe Gen1 and Gen2 interfaces.

7.4 Device Functional Modes

Table 1. Truth Table USB 3.0 SuperSpeed USB

SEL USB 3.0 PORT SELECTION
SSA0/1 SSB0/1 SSC0/1
0 To/From SSB0/1 To/From SSA0/1 Off
1 To/From SSC0/1 Off To/From SSA0/1

Table 2. Truth Table USB 2.0 High-Speed, Full-Speed, Low-Speed Path

HS_OE SEL USB 2.0 Port Selection
HSA HSB HSC
0 0 To/From HSB To/From HSA Off
0 1 To/From HSC Off To/From HSA
1 X Off Off Off