SNAS817C June 2021 – March 2023 HDC3020-Q1 , HDC3021-Q1 , HDC3022-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
An I2C controller will communicate to a desired target device through a target address byte. The target address byte consists of seven address bits and a direction bit that indicates the intent to execute a read or write operation. The HDC302x-Q1 features two address pins, which allow for supporting four addressable HDC302x-Q1 devices on a single I2C bus. Table 8-2 describes the pin logic levels used to communicate up to four devices. HDC302x-Q1 pins ADDR and ADDR1 must be set before any activity on the interface.
ADDR | ADDR1 | ADDRESS (Hex Representation) |
---|---|---|
Logic Low | Logic Low | 0x44 |
Logic Low | Logic High | 0x46 |
Logic High | Logic Low | 0x45 |
Logic High | Logic High | 0x47 |