SBOS014B September   2000  – January 2026 INA114

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Setting the Gain
      2. 6.1.2 Noise Performance
      3. 6.1.3 Offset Trimming
      4. 6.1.4 Input Bias Current Return Path
      5. 6.1.5 Input Common-Mode Range
      6. 6.1.6 Input Protection
      7. 6.1.7 Output Voltage Sense (SOIC-16 Package Only)
    2. 6.2 Typical Applications
  8. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • P|8
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

INA114 DW Package, 16-Pin SOIC (Top View) Figure 4-1 DW Package, 16-Pin SOIC (Top View)
INA114 P Package, 8-Pin PDIP (Top View) Figure 4-2 P Package, 8-Pin PDIP (Top View)