SBOSAG2 Data sheet

SBOSAG2 june 2023 INA351A

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DSG|8

Thermal pad, mechanical data (Package|Pins)

DSG|8
- QFND141I

Orderable Information

7.6 Typical Characteristics

at T_A = 25°C, V_S = (V+) – (V–) = 5.5 V, V_IN = (V_IN+) – (V_IN–) = 0 V, R_L = 10 kΩ, C_L = 10 pF, V_REF = V_S / 2, V_CM = [(V_IN+) + (V_IN–)] / 2 = V_S / 2, V_OUT = V_S / 2, V_{A_IN+} = V_S / 2, V_{A_OUT}= V_{A_IN-} and G = 10 (unless otherwise noted)

N = 36

μ = 23 μV

σ = 0.180 mV

Figure 7-1 Typical Distribution of Input Referred Offset Voltage

T_A = 25°C

N = 72

μ = 0.33 pA

σ = 0.43 pA

Figure 7-3 Typical Distribution of Input Bias Current

T_A = 85°C

N = 72

μ = 3.3 pA

σ = 0.53 pA

Figure 7-5 Typical Distribution of Input Bias Current

N = 36

μ = -0.30 μV/V

σ = 7.10 μV/V

Figure 7-7 Typical Distribution of CMRR

Figure 7-9 Input Referred Offset Voltage vs Temperature

Figure 7-11 Input Offset Current vs Temperature

Figure 7-13 Short Circuit Current vs Temperature

Figure 7-15 CMRR vs Temperature

V+ = 1.65 V and V– = –1.65 V

Figure 7-17 Input Referred Offset Voltage vs Input Common-Mode Voltage

V+ = 2.75 V and V– = –2.75 V

Figure 7-19 Input Offset Current vs Input Common-Mode Voltage

Figure 7-21 Input Referred Offset Voltage vs Supply Voltage

Figure 7-23 Output Voltage vs Output Current (Sourcing)

Figure 7-25 Closed-Loop Gain vs Frequency

Figure 7-27 PSRR+ (Referred to Input) vs Frequency

Figure 7-29 Input Referred Voltage Noise Spectral Density

Figure 7-31 Closed-Loop Output Impedance vs Frequency

V_S = 5.5 V	BW = 80 kHz	V_CM = 2.75 V
R_L = 10 kΩ	V_OUT = 0.5 V_RMS

Figure 7-33 THD + N Frequency

Figure 7-35 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

V+ = 2.75 V

V– = –2.75 V

V_OUT = 2 V_PP

Figure 7-37 Large Signal Step Response

V+ = 2.75 V

V– = –2.75 V

V_OUT = 2 V_PP

Figure 7-39 Large Signal Settling Time (Rising Edge)

V+ = 2.75 V

V– = –2.75 V

V_IN = 1 V_PP

Figure 7-41 Over-Load Recovery (Rising Edge)

V+ = 2.75 V

V– = –2.75 V

V_IN = 0.6 V_PP

Figure 7-43 No Phase Reversal

V_S = 5.5 V

Figure 7-45 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V_S = 5.5 V

Figure 7-47 Input Common-Mode Voltage vs Output Voltage

N = 36

μ = 0.23 μV/°C

σ = 0.36 μV/°C

Figure 7-2 Typical Distribution of Input Referred Offset Drift

T_A = 25°C

N = 36

μ = –0.40 pA

σ = 0.47 pA

Figure 7-4 Typical Distribution of Input Offset Current

T_A = 85°C

N = 36

μ = 0.05 pA

σ = 0.30 pA

Figure 7-6 Typical Distribution of Input Offset Current

N = 36

μ = 0.002 %

σ = 0.02 %

Figure 7-8 Typical Distribution of Gain Error

Figure 7-10 Input Bias Current vs Temperature

Figure 7-12 Quiescent Current vs Temperature

Figure 7-14 Gain Error vs Temperature

V+ = 2.75 V and V– = –2.75 V

Figure 7-16 Input Referred Offset Voltage vs Input Common-Mode Voltage

V+ = 2.75 V and V– = –2.75 V

Figure 7-18 Input Bias Current vs Input Common-Mode Voltage

V+ = 2.75 V and V– = –2.75 V

Figure 7-20 Quiescent Current vs Input Common-Mode Voltage

Figure 7-22 Quiescent Current vs Supply Voltage

Figure 7-24 Output Voltage vs Output Current (Sinking)

Figure 7-26 CMRR (Referred to Input) vs Frequency

Figure 7-28 PSRR– (Referred to Input) Vs Frequency

Figure 7-30 0.1 Hz to 10 Hz Voltage Noise in Time Domain

Figure 7-32 Maximum Output Voltage vs Frequency

V_S = 5.5 V	BW = 80 kHz	V_CM = 2.75 V
R_L = 100 kΩ	V_OUT = 1 V_RMS

Figure 7-34 THD + N Frequency

V_S = 5.5 V

V_OUT = 100 mV_PP

Figure 7-36 Small-Signal Overshoot vs Capacitive Load

V+ = 2.75 V

V– = –2.75 V

V_OUT = 2 V_PP

Figure 7-38 Large Signal Settling Time (Falling Edge)

V+ = 2.75 V

V– = –2.75 V

V_OUT = 0.1 V_PP

Figure 7-40 Small-Signal Step Response

V+ = 2.75 V

V– = –2.75 V

V_IN = 1 V_PP

Figure 7-42 Over-Load Recovery (Falling Edge)

V_S = 3.3 V

Figure 7-44 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V_S = 3.3 V

Figure 7-46 Input Common-Mode Voltage vs Output Voltage