SBOS914F October   2018  – April 2021 INA592

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: G = 1/2
    6. 7.6 Electrical Characteristics: G = 2
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Basic Power Supply and Signal Connections
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Operating Voltage
          2. 9.2.1.2.2 Offset Voltage Trim
          3. 9.2.1.2.3 Input Voltage Range
          4. 9.2.1.2.4 Capacitive Load Drive Capability
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Additional Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.2.2 Offset Voltage Trim

The INA592 is production trimmed for low offset voltage and drift. Most applications require no external offset adjustment. Figure 9-2 shows an optional circuit for trimming the output offset voltage. The output is referred to the output reference terminal (pin 1), which is normally grounded. A voltage applied to the REF pin is summed with the output signal. This summing operation can be used to null offset voltage. To maintain good common-mode rejection, the source impedance of a signal applied to the REF pin must be less than 8 Ω. For low impedance at the REF pin, the trim voltage can be buffered with an op amp, such as the OPA177.

GUID-D5C24CF4-B677-47F7-BE26-FB2B6AB31BD6-low.gifFigure 9-2 Offset Adjustment