SBOS914F October   2018  – April 2021 INA592

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: G = 1/2
    6. 7.6 Electrical Characteristics: G = 2
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Basic Power Supply and Signal Connections
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Operating Voltage
          2. 9.2.1.2.2 Offset Voltage Trim
          3. 9.2.1.2.3 Input Voltage Range
          4. 9.2.1.2.4 Capacitive Load Drive Capability
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Additional Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics: G = 1/2

at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to ground (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE (RTO)(1)
VOS Input offset voltage RTO, VS = ±2.25 V to ±3 V, VCM = –3 V ±14 ±40 µV
RTO, VS = ±3 V to ±18 V ±14 ±40
dVOS/dT Input offset voltage drift ±0.7 ±2.0 µV/°C
PSRR Power-supply rejection ratio VS = ±3 V to ±18 V ±0.5 ±5 µV/V
INPUT VOLTAGE
VCM Common-mode voltage VO = 0 V 3[(V–)–0.1]
–2VREF 		3(V+)–2VREF V
CMRR Common-mode rejection ratio RTO, 3 [(V−) – 0.1 V)]
≤ VCM ≤ 3 [(V+) – 3 V]		 88 100 dB
TA = –40°C to +125°C 82 90
RTO, 3 [(V+) – 1.5 V)]
≤ VCM ≤ 3 [(V+))]		 88 100
TA = –40°C to +125°C 72 90
INPUT IMPEDANCE(2)
zid Differential  VO = 0 V 24 kΩ
zic Common-mode 9 kΩ
GAIN
G Initial 1/2 V/V
GE Gain error VO = –10 V to +10 V, VS = ±15 V ±0.01 ±0.03 %
Gain drift(3) ±0.2 ±0.5 ppm/°C
Gain nonlinearity VO = –10 V to +10 V, VS = ±15 V 1 ppm
OUTPUT
VO Output votlage swing Positive rail (V+) – 170 (V+) – 220 mV
Negative rail (V−) + 190 (V−) + 220
ISC Short-circuit current ±65 mA
NOISE
En Output voltage noise f = 0.1 Hz to 10 Hz, RTO 3 μVpp
en Output voltage noise density f = 1 kHz, RTO 18 nV/√Hz
FREQUENCY RESPONSE
BW Small-signal –3 dB- bandwidth 2.0 MHz
SR Slew rate 18 V/µs
tS Settling time To 0.1% of final value, VO = 10-V step 1 µs
To 0.01% of final value, VO = 10-V step 1.3
THD+N Total harmonic distortion + noise f = 1 kHz, VO = 2.8 VRMS 0.00038 %
Noise floor, RTO 80-kHz bandwidth, VO = 3.5 VRMS –116 dB
tDR Overload recovery time 200 ns
POWER SUPPLY
IQ Quiescent current IO = 0 mA 1.1 1.2 mA
TA = –40°C to +125°C 1.5 mA
(1) Includes effects of input bias and offset currents of amplifier.
(2) Resistors are ratio matched but have ±20% absolute value.
(3) Specified by wafer test to 95% confidence level.