SBAS738A June   2018  – October 2018 ISO224

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Input Clamp Protection Circuit
      3. 8.3.3 Isolation Channel Signal Transmission
      4. 8.3.4 Fail-Safe Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Detailed Design Procedure

The high-side power supply (VDD1) for the device is generated with a suitable isolated power source. An example of such a circuit is provided in the Power Supply Recommendations section.

The floating ground reference (GND1) is derived from one of the ends of the shunt resistor that is connected to the negative input of the device (VINN). If a four-pin shunt is used, the inputs of the device are connected to the inner leads and GND1 is connected to one of the outer shunt leads.

Use Ohm's Law to calculate the minimum total resistance of the resistive divider to limit the cross current IAC to the desired value: R1 + R2 = VAC / IAC. The input voltage at the ISO224 results from the resistance ratio of R1 and R2 and the actual AC voltage: VIN = VAC x R2 / (R1 + R2).

Consider the following two restrictions to choose the proper value of the R1 and R2 resistors:

  • The voltage drop on R2 caused by the nominal AC voltage range of the system must not exceed the recommended input voltage range VIN of the ISO224
  • The voltage drop on R2 caused by the maximum allowed system overvoltage must not exceed the input voltage that causes a clipping output: VIN ≤ VClipping

Table 2 lists examples of nominal E96-series (1% accuracy) resistor values for AC systems using 120 V, 240 V, and 400 V as nominal voltages.

Table 2. Resistor Value Examples

PARAMETER 120-VAC SYSTEM 240-VAC SYSTEM 400-VAC SYSTEM
Resistive divider resistor R1 115 kΩ 237 kΩ 392 kΩ
Resistive divider resistor R2 12.7 kΩ 12.4 kΩ 12.1 kΩ
Resulting current through resistive divider IAC 0.93 mA 0.93 mA 0.98 mA
Resulting input voltage VIN ±11.934 V ±11.933 V ±11.977 V

For systems using single-ended input ADCs with a 5-V supply, Figure 48 shows an example of a TLV6001-based signal conversion and filter circuit. Tailor the bandwidth of this filter stage to the bandwidth requirement of the system and use NP0-type capacitors for best performance.

ISO224 ai_output_bas738.gifFigure 48. Connecting the ISO224 Output to a Single-Ended Input 5-V ADC

For systems using single-ended, ±10-V input ADCs, the ISO224EVM offers a signal path based on an OPA277 that converts the differential output of the ISO224 and limits the signal bandwidth to 50 kHz.

For more information on the general procedure to design the filtering and driving stages of SAR ADCs, consult the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power TI Precision Designs, available for download at www.ti.com.