SLLSEF1B September 2013 – August 2015 ISO7142CC
The isolator in Figure 12 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
50 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.
|DTI||Distance through the insulation||Minimum internal gap (internal clearance)||0.014||mm|
|CI(2)||Input capacitance||VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V||2||pF|
|DIN V VDE V 0884-10 (VDE V 0884-10):2006-12|
|VIOTM||Maximum transient isolation voltage||4242||VPK|
|VIORM||Maximum working isolation voltage||566||VPK|
|VPR||Input-to-output test voltage||After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
|Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial discharge < 5 pC
|Method b1, 100% production test,
VPR = VIORM x 1.875, t = 1 s,
Partial discharge < 5 pC
|L(I01)||Minimum air gap (clearance)||Shortest terminal to terminal distance through air||3.7||mm|
|L(I02)||Minimum external tracking (creepage)||Shortest terminal to terminal distance across the package surface||3.7||mm|
|CTI||Tracking resistance (comparative tracking index)||DIN EN 60112 (VDE 0303-11); IEC 60112||≥400||V|
|RIO(1)||Isolation resistance, input to output||VIO = 500 V, TA = 25oC||>1012||Ω|
|VIO = 500 V, 100oC ≤ TA ≤ 125oC||>1011|
|VIO = 500 V, TS = 150oC||>109|
|CIO(1)||Barrier capacitance, input to output||VI = 0.4 sin (2πft), f = 1 MHz||2.4||pF|
|VISO||Withstanding Isolation voltage||VTEST = VISO= 2500 VRMS, 60 sec (qualification);
VTEST = 1.2 * VISO= 3000 VRMS, 1 sec (100% production)
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
|Installation classification / Overvoltage Category for Basic Insulation||Rated mains voltage ≤ 150 VRMS||I–IV|
|Rated mains voltage ≤ 300 VRMS||I–III|
|Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07||Certified under UL 1577 Component Recognition Program||Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1||Certified according to GB 4943.1-2011|
Maximum transient Isolation IsolatiIsolationvoltage, 4242 VPK
Maximum working isolation voltage, 566 VPK
|Single protection, 2500 VRMS(1)|| 3000 VRMS Isolation rating;
185 VRMS Reinforced Insulation and 370 VRMS Basic Insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2;
150 VRMS Reinforced Insulation and 300 VRMS Basic Insulation per CSA 61010-1-12 and IEC 61010-1 3rd Ed.
|Basic Insulation, Altitude ≤ 5000m, Tropical climate, 250 VRMS maximum working voltage.|
|File number: 40016131||File number: E181974||Master contract number: 220991||Certificate number: CQC14001109540|
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
|IS||Safety input, output, or supply current||DBQ-16||θJA = 104.5°C/W, VI = 5.5V, TJ = 150°C, TA = 25°C||217||mA|
|θJA = 104.5°C/W, VI = 3.6V, TJ = 150°C, TA = 25°C||332|
|θJA = 104.5°C/W, VI = 2.7V, TJ = 150°C, TA = 25°C||443|
|TS||Maximum safety temperature||150||°C|
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
|PU||PU||H||H or open||H|
|L||H or open||L|
|Open||H or open||H|
|PD||PU||X||H or open||H|