SLLSEK8C January   2015  – April 2015 ISO7320C , ISO7320FC , ISO7321C , ISO7321FC


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, 5 V
    6. 6.6 Electrical Characteristics, 3.3 V
    7. 6.7 Switching Characteristics, 5 V
    8. 6.8 Switching Characteristics, 3.3 V
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Voltage Feature Description
        1. Insulation and Safety-Related Specifications for D-8 Package
        2. Insulation Characteristics
        3. Regulatory Information
        4. Safety Limiting Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. Typical Supply Current Equations
      2. 9.2.2 Detailed Design Procedure
        1. Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Performance Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 PCB Material
    2. 11.2 Layout Guidelines
    3. 11.3 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The isolator in Figure 14 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25 Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.

In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can be either above or below the common mode voltage VREF depending on whether the input bit transitioned from 0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL) at the output of the HF channel comparator measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.

8.2 Functional Block Diagram

ISO7320C ISO7320FC ISO7321C ISO7321FC internal_block_sllsei8.gif
Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.

8.3 Feature Description

ISO7320C Same 3000 VRMS / 4242 VPK(1) 25 Mbps High
ISO7320FC Low
ISO7321C Opposite High
ISO7321FC Low
(1) See the Regulatory Information section for detailed Isolation Ratings

8.3.1 High Voltage Feature Description Insulation and Safety-Related Specifications for D-8 Package

over recommended operating conditions (unless otherwise noted)
L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4 mm
L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4 mm
CTI Tracking resistance (comparative tracking index) DIN EN 60112 (VDE 0303-11); IEC 60112 400 V
DTI Minimum internal gap (internal clearance) Distance through insulation 13 µm
RIO Isolation resistance, input to output(1) VIO = 500 V, TA = 25°C 1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C 1011 Ω
CIO Isolation capacitance, input to output(1) VIO = 0.4 sin (2πft), f = 1 MHz 1.5 pF
CI Input capacitance(2) VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 1.8 pF
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.


Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.

Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. Insulation Characteristics

over recommended operating conditions (unless otherwise noted)
VIOWM Maximum isolation working voltage 400 VRMS
VIORM Maximum repetitive peak voltage per
DIN V VDE V 0884-10
566 VPK
VPR Input-to-output test voltage per
DIN V VDE V 0884-10
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680 VPK
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
VIOTM Maximum transient overvoltage per
DIN V VDE V 0884-10
t = 60 sec (qualification)
t= 1 sec (100% production)
4242 VPK
VIOSM Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM = 7800 VPK (qualification)
6000 VPK
VISO Withstand isolation voltage per UL 1577 VTEST = VISO = 3000 VRMS, t = 60 sec (qualification);
VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100% production)
3000 VRMS
RS Insulation resistance VIO = 500 V at TS >109 Ω
Pollution degree 2
(1) Climatic Classification 40/125/21

Table 1. IEC 60664-1 Ratings Table

Basic isolation group Material group II
Installation classification Rated mains voltage ≤ 150 VRMS I–IV
Rated mains voltage ≤ 300 VRMS I–III Regulatory Information

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1 Recognized under UL 1577 Component Recognition Program Certified according to GB4943.1-2011
Basic Insulation
Maximum Transient Overvoltage, 4242 VPK
Maximum Surge Isolation Voltage, 6000 VPK
Maximum Repetitive Peak Voltage, 566 VPK
400 VRMS Basic Insulation and 200 VRMS Reinforced Insulation working voltage per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2;
300 VRMS Basic Insulation working voltage per CSA 61010-1-12 and IEC 61010-1 3rd Ed.

Single protection, 3000 VRMS(1) Basic Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage
Certificate number: 40016131 Master contract number: 220991 File number: E181974 Certificate number: CQC15001121656
(1) Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577. Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
IS Safety input, output, or supply current RθJA = 121 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 188 mA
RθJA = 121 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 287
TS Maximum case temperature 150 °C

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolut Maximun Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

ISO7320C ISO7320FC ISO7321C ISO7321FC D011_SLLSEK8.gifFigure 15. θJC Thermal Derating Curve per DIN V VDE V 0884-10

8.4 Device Functional Modes

Table 2. Function Table(1)

ISO7320C, ISO7321C ISO7320FC, ISO7321FC
Open H(2) L(3)
PD PU X H(2) L(3)
X PD X Undetermined Undetermined
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level; Open = Not connected
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level

8.4.1 Device I/O Schematics

ISO7320C ISO7320FC ISO7321C ISO7321FC device_IO_sllsek8.gifFigure 16. Device I/O Schematics