SLLSEU0C November   2016  – February 2020 ISO7740-Q1 , ISO7741-Q1 , ISO7742-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Description Continued
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Rating
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—5-V Supply
    10. 7.10 Supply Current Characteristics—5-V Supply
    11. 7.11 Electrical Characteristics—3.3-V Supply
    12. 7.12 Supply Current Characteristics—3.3-V Supply
    13. 7.13 Electrical Characteristics—2.5-V Supply
    14. 7.14 Supply Current Characteristics—2.5-V Supply
    15. 7.15 Switching Characteristics—5-V Supply
    16. 7.16 Switching Characteristics—3.3-V Supply
    17. 7.17 Switching Characteristics—2.5-V Supply
    18. 7.18 Insulation Characteristics Curves
    19. 7.19 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
        1. 10.2.3.1 Insulation Lifetime
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBQ|16
  • DWW|16
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
DWW-16 DW-16 DBQ-16
CLR External clearance(1) Shortest terminal-to-terminal distance through air >14.5 >8 >3.7 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface >14.5 >8 >3.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 >21 >21 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >600 >600 >600 V
Material group According to IEC 60664-1 I I I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300 VRMS I-IV I-IV I-III
Rated mains voltage ≤ 600 VRMS I-IV I-IV n/a
Rated mains voltage ≤ 1000 VRMS I-IV I-III n/a
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2828 2121 566 VPK
VIOWM Maximum working isolation voltage AC voltage; Time dependent dielectric breakdown (TDDB) Test; see Figure 30 2000 1500 400 VRMS
DC voltage 2828 2121 566 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 × VIOTM,
t= 1 s (100% production)
8000 8000 4242 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000 8000 4000 VPK
qpd Apparent charge(4) Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5 ≤5 ≤5 pC
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5 ≤5 ≤5
Method b1; At routine test (100% production) and preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5 ≤5 ≤5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz ~1 ~1 ~1 pF
RIO Isolation resistance(5) VIO = 500 V, TA = 25°C >1012 >1012 >1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 >1011 >1011
VIO = 500 V at TS = 150°C >109 >109 >109
Pollution degree 2 2 2
Climatic category 55/125/
21
55/125/
21
55/125/
21
UL 1577
VISO Maximum withstanding isolation voltage VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)
5700 5000 3000 VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.