SWRS212B May 2017 – April 2018 IWR1642
Refer to the PDF data sheet for device specific package drawings
The supports four differential LVDS IOs/Lanes. The lane configuration supported is two Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data rates:
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.